imec.academy

Broaden your mind, strenghten your skills.


Imec.academy is the learning institute for imec's own employees and for the local and international industry and academia. Imec.academy offers high-level technical training programs which combine world-class expertise with hands-on applications. 

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27-29 March 2017

Introduction to nanoscale CMOS technology

Get an overview of the state of the art CMOS process flow.


This course covers the general CMOS process flow, how a circuit is manufactured starting from a clean wafer up to a final circuit ready for test, dicing and packaging.


Challenges for the general process flow and for the different process modules will be discussed.

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21 April 2017

Workshop on Characterization and Metrology for 3D CMOS

The continued CMOS scaling is challenging and pushing the limits of existing characterization and metrology techniques. 3DAM and METRO4-3D are EU-funded pathfinding and assessment projects focusing on innovations and progress in metrology related to the latest generation of 3D FEOL and BEOL structures (fins, nanowires, TSVs) as well as 2D materials:

 

  • Dimensional metrology: 3D-AFM, CD-SEM, OCD
  • Structural analysis: TEM tomography, CL, SHG, GHz-SAM, X-ray CT
  • Compositional/dopant analysis: SIMS, Atom probe, STEM-EDX and EELS, IRR, Raman, HRXRD
  • Carrier distribution and mobility: 3D-SSRM, micro-multi-point probes, THz spectroscopy
  • Strain and stress: HRXRD, Raman, PED

 

The goal of this workshop is to disseminate the results of the projects to the public. The combination with the insights and learnings from experts will make this one-day workshop an up-to-date overview of the most recent advances in the analytical techniques and diagnostic capabilities essential for technology development.

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8-10 May 2017

Silicon Photonics Training

This course provides an overview of fabless manufacturing of Photonics Integrated Circuits (PICs) and introduces design flow for PICs through hands-on training on photonic design automation tools.

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12-16 June 2017

VHDL language and design flow

This 5-day course 'VHDL language and design flow' is centered on VHDL syntax (through example) while emphasizing good code style and the link to hardware.


The increasing complexity of digital circuits brings the need for a design methodology that allows a short design cycle, while maintaining architectural flexibility, re-use of IP blocks and easy documentation. 

VHDL is a standard worldwide language for the design, documentation and description of electronic systems on the component, board or system level. It supports design verification through simulation and design creation through synthesis. 

Simulation and synthesis are however not the only tools used in the design flow of an ASIC. Digital frontend designers nowadays need also knowledge about a whole set of tools like e.g. static timing analysis, test insertion, power analysis and testpattern generation.

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11-13 September 2017

Introduction to nanoscale CMOS technology

Get an overview of the state of the art CMOS process flow.


This course covers the general CMOS process flow, how a circuit is manufactured starting from a clean wafer up to a final circuit ready for test, dicing and packaging.


Challenges for the general process flow and for the different process modules will be discussed.

View more info and sessions

24-27 October 2017

Advanced digital physical implementation flow (feat. low-power)

Are you interested in the changes introduced in the IC design flow for advanced deep-submicron technology nodes? Are you searching for a deeper understanding of the low-power issues? Do you want to know everything about relevant process parameters and IP-libraries? Or do you want to become familiar with future design flow challenges? A hands-on course with experts who daily face the do's-and-don'ts in physical design will bring you to the next level. State-of-the-art EDA tools and relevant design exercises in the 65-40nm technology bring you to a more advanced level of implementation skill.

 

State-of-the-art EDA tools and relevant design exercises will bring the participants to a level at which they can confidently face future design flow challenges introduced by the 65 nm process characteristics and constraints.

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13-17 November 2017

Nanoscale CMOS process technology

This course offers a comprehensive, advanced state-of-the art training overview in the practice, fundamentals and emerging trends of silicon wafer processing focussed on deep submicron CMOS devices.
 

During the course there will be ample time to explore the new technologies and to study the trade-offs among various approaches and options.
 

Get a good overview of state-of-the-art deca-nanometer CMOS process technology.

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20-23 November 2017

Reliability and failure mechanisms in advanced CMOS technologies

Learn about the physics for failure mechanism in advanced CMOS technology.
 

A course taught by the experts actively involved in research in the field of advanced CMOS reliability.

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