ADC ( Analog Digital Converter ) 6bit 2.2 GS/s

This 2.2 GS/s 6 bit 2.6 mW 4 times interleaved fully dynamic pipelined SAR ADC in 40 nm CMOS is ideal for communication in the 60 GHz band.

Macro Name  ADC ( Analog Digital Converter ) 6bit 2.2 GS/s
Short Description(max 128 characters)  This 2.2 GS/s 6 bit 2.6 mW 4 times interleaved fully dynamic pipelined SAR ADC in 40 nm CMOS is ideal for communication in the 60 GHz band.
Extra description (optional) Imec offers a white-box IP license with support on a 2.2 GS/s 6 bit 2.6 mW 4 times interleaved fully dynamic pipelined SAR (Successive Approximation Register) ADC in 40 nm digital CMOS. Such a fast ADC with low resolution is ideal for communication in the unlicensed frequency band around 60 GHz. Dynamic pipelined conversion enables low power quantization at high speed with low input capacitance but requires calibration. A folding front-end halves the calibration effort. This ADC achieves a SNDR of 31.1 dB at low frequencies, reducing till 26.2 dB at 3.5 GS/s at Nyquist frequency. The energy per conversion step is 40 fJ up till 2.2 GS/s.
Market category Communications - Data processing - Consumer Electronics
Possible applications & standards This ADC is a good candidate for next generation Software Defined Radio ( SDR ) receivers, including LTE Advanced and the emerging generation of WIFI IEEE 802.11ac.
Primary Category  Analog & Mixed Signal IP:A2D Converter
Node / process 40nm Low Power CMOS
Foundry  TSMC
Maturity  Silicon proven on prototypes, hence only white-box license (no corner characterization performed for high volume production)
Leaflet or datasheet URL  
Conference where this IP has been published ISSCC2010
Paper publication URL Download the paper publication here
Chip area(for Hard IP only) (um**2) 30000
Width (for Hard IP only) (um) 120 um
Height (for Hard IP only) (um) 250 um
Power (uW/MHz) 1.15 uW/MHz
Constant Power (mW) 2.6 mW @ 2.2 GS/s
Constant Leakage Power (uW) < 20 uW
Features
  • ADC in 40nm digital CMOS
  • 2.2 GS/s
  • 6 bit
  • low power 2.6 mW
  • dynamically pipelined SAR (Successive Approximation Register)
  • 4x interleaved
  • SNDR of 31.1 dB at low frequencies, SNDR of 26.2 dB at 3.5 GS/s at Nyquist frequency
  • energy 40 fJ/conversion step at 2.2 GS/s and Nyquist frequency
  • calibrated INL/DNL for each channel is below 0.8 LSB for a 10 mV LSB
  • 0.03 mm**2 core chip area
Deliverables
  • whitebox IP license with technology transfer training and support
  • evaluation boards with ADC samples