PhD researcher on A sequential 3D implementation for neuromorphic processing element

Leuven - PhD
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More than two weeks ago
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The primary component for a neuro-computing architectures and artificial neural networks has tight constraints on extremely low-power consumption features and their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. The primary objective of this project is to explore, analyze and develop a sequential 3D based circuit block element that can be efficiently be used as synaptic element in the neuromorphic computing domain. The proposed solution should be scalable in nature.

The PhD work would involve coming up with novel heterogeneously integrated component to enable an efficient neuromorphic hardware implementation in terms of performance, power and area. The student has to explore, analyze and evaluate the benefits of neuromorphic hardware in different application domain. His/her work will involve cross-domain interaction from manufacturing technology to circuit design and system architecture.

The student will start from an in-house developed device solutions for Non-volatile memory and early idea on heterogeneous sequential 3D integration of logic and memory. He or she can rely on the imec-expertise of memory devices, having expertise in processing, characterization and simulation/modeling, as well as on the expertise of the physics modeling and simulation team. The student will get experimental data from the memory team for model verification. Eventual goal would be to create a prototype synaptic element for the neuromorphic computing.

Required background: Electrical and computer engineering with CMOS design background, preferable in the context of memory design. Previous experience with microarchitecture, MATLAB, C/C++ programming would help. Good understanding of device architecture is preferred.

Type of work:

20% literature, 40% design, 40% modeling.

Supervisor: Rudy Lauwereins

Co-supervisors: Nadine Collaert and Gouri Sankar Kar

Daily advisor: Arindam Mallik and Sushil Sakhare

When you apply for this PhD project, mention the following reference code in the imec application form: ref. STS 1704-17.

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