The goal of this PhD topic is to develop an advance digital polar RF receiver for IoT applications. Ultra-low power consumption and digital-intensive low-cost design are two of the most critical requirements of the integrated RF transceivers. Conventional wireless receivers adopt “Cartesian” I/Q architectures, which perform frequency down-conversion, channel selection and digitization in two separated I/Q channels. The I/Q channel mismatch, DC offset and high power consumption are the primary disadvantages of the Cartesian receivers.
Constant-envelope FSK-type modulation is widely adopted in IoT, e.g., HS-OQPSK in IEEE802.15.4 and GFSK in BLE, for its low complexity (de)modulation, which is favored in ULP implementations. Several energy-efficient “phase-domain” FSK RXs were developed to leverage the constant-envelope nature. E.g., the phase-tracking RX use the principal of “phase-locking loop (PLL)” to extract the frequency modulated information directly at the carrier. They also have addition advantages of small die area and no I/Q mismatch.
On the other hand, more and more emerging IoT standards use non-constant envelope modulations, e.g., /4-QPSK in Narrowband-IoT, to increase its spectral efficiency. The PhD in this project will evolve the phase-tracking receivers to a “polar” receiver, which can demodulate both phase and amplitude information, meanwhile keep the phase-tracking receiver’s advantage of single channel, low-power consumption and low die area.
Required background: Solid background in RF and analog integrated circuit design, preferably with sufficient experience in tape-out and lab evaluation.
Type of work: RF architecture innovation, RF integrated circuit design.
Supervisor: Piet Wambacq
Co-Supervisor: Guido Dolmans
Supervisor KU Leuven:
Imec-BE supervisor: Dr. Jan Craninckx
imec-NL supervisors : Dr. Yao-Hong Liu
When you apply for this PhD project, mention the following reference code in the imec application form: ref. SE 1704-02.