PhD researcher on Exploratory devices for nonvolatile, low power, and ultrafast magnetic memories

Leuven - PhD
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More than two weeks ago
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There is considerable interest in electrically controlling nano-magnets (Spintronic) in order to develop non-volatile magnetic memories (MRAM) [1]. Indeed, the microelectronics industry is facing major challenges related to the volatility of CMOS cache memory elements (usually SRAM and eDRAM). Due to decreasing devices size, leakage current in standby mode are now dominating the power dissipation of CMOS circuits. Furthermore, the increased density and reduction in die area lead to heat dissipation and reliability issues. Integration of non‐volatility in memory hierarchy would solve these issues by incredibly minimizing static power consumption. MRAMs are among most credible candidates that are low power and fast enough to compete with SRAM and replace them at cache level. Most advanced MRAM devices are magnetic tunnel junctions (MTJ) that consist of two ferromagnetic layers separated by a very thin oxide barrier, one of the layer being the storage layer, the other is used as reference layer. Depending on the relative orientation of the magnetization of these two layers (parallel/ anti-parallel), the MTJ cell will exhibit low/high resistance through the tunnel magneto-resistance effect (TMR), defining the reading state (0/1). The writing operation relies on Spin Transfer Torque (STT)[1], which is the transfer of spin angular momentum from the reference layer to the free layer that in the end can switch reversibly the storage layer between two stable states (defined by its magnetic anisotropy). Though, STT-MRAM requires to inject large current across the oxide barrier for writing, which results in reliability and endurance issues at very fast operations, while it is a critical aspect for SRAM and DRAM replacement. Spin-Orbit Torque (SOT)[2,3] is an alternative spin current source originating from the spin-orbit interaction and mediated by Spin Hall[4] and Rashba[5] interactions - the exact underlying physics is complex and still deeply discussed in the literature. SOT distinguishes by offering the possibility to switch magnetization using in-plane currents[2], unlike STT that requires a current flow in the perpendicular direction through MTJ. That allows for decoupling reading (TMR) and writing (SOT) path and this new 3-terminal geometry naturally solves the oxide barrier breakdown issue of the STT-MTJ. The proof of concept of such SOTMRAM was recently confirmed[6], and robust deterministic magnetization reversal at sub-ns scale was demonstrated[7]. SOT-MRAM seem therefore a promising solution for SRAM replacement in cache memory, even though some challenges have to be tackled before full integration in future technology nodes can be envisaged.

The PhD research activity will first focus to address two key issues of SOT-MTJ in order to demonstrate integration feasibility: i. writing current is still outsized for applications and its decrease will go through the use of large SOT metals (W, Pt, Ta...), and by developing new materials aiming at even larger SOT, ii. SOT mechanism requires the application of an external field in order to break the symmetry of the system and to obtain deterministic switching[2], but recent publications paved new ways for the realization of field-free switching SOT-MTJ, for example by converting this external field in internal field through the use of antiferromagnetic materials[8,9]. MTJs properties are very sensitive to stack composition, and a first challenge of the thesis is to succeed in incorporating these new materials while maintaining MTJs benchmark characteristics. To this aim, the candidate will benefit from the expertize of imec in developing new materials and manufacturing high quality MTJ devices. The second challenge is to demonstrate sub-ns switching at 0-field, the final goal being to integrate such devices in a memory demonstrator. Other novel magnetization switching mechanism will also be studied during the thesis.

The thesis work will be part of the Exploratory memory project of imec. It has ambitious objectives, and will require to cover a broad area of competences: fundamentals of magnetism, spintronic and SOT physics, development of new tools for rapid screening of SOT magnitude in studied layers, structural and magnetic characterization, 300mm integration of SOT-MTJ cells and their electrical characterization, and finally device modeling of observed behaviors (micromagnetic simulations). The PhD applicant should therefore have a strong interest and motivation to understand the underlying physics, keeping the application in mind, and be willing to perform extensive fabrication and characterization work. Interested candidates should contact K. Garello for more ample information.

[1] C. Chappert et al., Nature Material (2007), [2] M. Miron et al., Nature (2011); [3] K. Garello et al., Nature Nanotech (2013); [4] V.I. Perel et al., JETP Lett (1971); [5] Rashba et al., JEPT (1984); [6] M. Cubucku et al., APL (2014); [7] K. Garello et al., APL (2014), [8] F. Fukami et al., Nature Materials (2016), [9] A. van den Brink et. al, Nature Comm. (2016)

Required background: 

Spintronic and magnetism physics, material science.

Type of work:

80% experimental work (nano-fabrication, electrical characterization, development of new characterization tools), 10% physics- and device-based modeling, 10% literature.

Supervisor: Jo De Boeck and Bart Sorée

Daily advisor: Kevin Garello and Bart Sorée

When you apply for this PhD project, mention the following reference code in the imec application form: ref. STS 1704-05.

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