PhD researcher on High-speed ADCs for millimeter-wave applications

Leuven - PhD
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More than two weeks ago
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Because of the never-ending increase in the consumer’s need for higher data rates, fifth generation (5G) cellular systems are currently being standardized. These will offer a 1000X improvement w.r.t. 4G systems, by serving more users simultaneously, at data rates of several Gbps. That is achieved by using spectrum in the millimeter-wave range, at e.g. 28 or 60GHz, where several GHz of bandwidth is available. So both the RF carrier frequency and the channel or baseband bandwidth are an order of magnitude higher than before, posing obviously extreme challenges on the transceiver design.

Simultaneously, many other applications are also developing in this frequency range.  High-accuracy digital radars for e.g. self-driving cars pose similar challenges. They operate in the 79GHz band, and the radar resolution improves linearly with the RF bandwidth, so also here the term ‘baseband’ does not apply anymore, since it spans up to several GHz.

In this PhD, the topic of high-performance analog-to-digital converters (ADC) in this context will be dealt with. In recent years, several circuit-level and architectural innovations have been reported that been able to substantially lower the power consumption of ADCs typically used in wireless and other systems. A similar breakthrough is needed to realize low-power ADCS with sampling rates of up to 10GS/s.

And sampling speed is not the only challenge, also the resolution must be improved to an accuracy of 10 bits or more.  In communication system, this is needed because higher-order modulation schemes are used to increase data rate, as well as requirements for a better interference resilience. Radar systems are simultaneously transmitting and receiving, so they need a high dynamic range to detect small desired inputs in the presence of the large transmitted signal.

In this project, imec is looking for a motivated and innovative PhD student that will take up this challenge. The high speed potential of modern nanoscale performance must be exploited to achieve these very high bandwidths, but this will not be possible without significant innovation in both ADC architectures and detailed building block implementation. Deep knowledge of both possibilities and the limitation of the technology’s devices (transistors and passive), combined with the art of analog design and digital and mixed-mode calibration loops can advance the state of the art in this field.

Required background: 

Electrical engineering, analog integrated circuits.

Type of work:

System study, integrated circuit design & layout, measurements.

Supervisor: Piet Wambacq

Daily advisor: Jan Craninckx

When you apply for this PhD project, mention the following reference code in the imec application form: ref. SE 1704-03.

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