PhD researcher on Hot-carrier degradation in 3D vertical CMOS VLSI technologies

Leuven - PhD
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More than two weeks ago
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Several directions have been pursued by the semiconductor industry in the past decade.  i) Conventional Si and SiO2 are being replaced by more exotic materials, from high-k gate dielectrics to metal gates and to high-mobility substrates,  ii)  new transistor architectures are being introduced,  iii)  transistor are downscaled toward atomic dimensions with each stochastically-behaving gate oxide defect potentially having a substantial impact on the device operation, while  iv) supply voltages are reduced; nonetheless, electric fields are increasing.  Recently, in order to maintain the trend of ever-increasing performance, the semiconductor industry is also considering v) 3D integration options. 

All of these developments constitute new challenges for ensuring sufficient reliability, i.e., limited degradation during operation, of the devices based on such advanced CMOS VLSI technologies.  In particular, the latter trend of 3D integration, especially with complementary horizontal stacked or vertical nanowires, brings additional reliability challenges.   Nanowire transistors with very short channels, operating in the near-ballistic regime, are expected to undergo severe hot-carrier degradation, resulting in charging of preexisting defects in the gate dielectrics and simultaneous generation of new defects.  This will be compounded by significant channel temperature increases due to “self-heating” of the nanowire transistors from the passing currents and close packing of the devices in all 3 dimensions.

The thesis work will rely on designing, simulating,  and measuring dedicated test structures (both individual devices to extract acceleration trends and large arrays to obtain degradation distributions), ultimately aiming to deconvolute and to understand the contributions of individual mechanisms contributing to hot carrier degradation. The subsequent challenge of this Thesis will then be developing physics-based degradation models for all mechanisms and coupling them self-consistently.

Required background: 

Semiconductor device physics, electrical measurements, programming.

Type of work:

10% literature, 10% design and layout, 40% experimental work, 40% modeling and simulations.

Supervisor: Guido Groeseneken

Daily advisor: Ben Kaczer

When you apply for this PhD project, mention the following reference code in the imec application form: ref. STS 1704-03.

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