Over the past 15 years, substantial progress has been made in silicon-based photonic integration platforms. Using highly-confined Si waveguides, the footprint of photonic ICs has been dramatically reduced which has enabled e.g. CMOS compatible high-density electro-optic transceivers for short-reach optical interconnects. Contemporary Si photonic platforms use mostly group IV elements (Si and Ge) for the realization of active devices (modulators and photodetectors). However, there’s an increasing interest in monolithic integration of III-V materials for realizing superior active device functionality, including on-chip light emission and improved modulation and detection capability.
In this thesis, the PhD candidate will develop and benchmark different device architectures for realizing highly sensitive photoreceivers on silicon targeting next-generation low-power optical interconnects. Several device concepts including III-V p-i-n photodetectors, avalanche photodetectors and phototransistors will be considered. Advanced TCAD modeling will be used to optimize device performance, including responsivity, opto-electrical bandwidth, noise and dark current. Both waveguide and surface illuminated photoreceivers will be pursued. The most promising device concepts will be implemented in imec’s emerging monolithic III-V on Si platform, using a combination of 300mm wafer scale processes and lab-based post processing.
Physics, electrical engineering.
Type of work:
5% literature survey, 20% simulation, 10% design and layout, 30% lab device processing, 30% device characterization, 5% reporting.
Daily advisor: Marianna Pantouvaki
When you apply for this PhD project, mention the following reference code in the imec application form: ref. STS 1704-11.