As the transistor device dimensions approach the atomic scale, the traditional scaling of CMOS technology described by the renown Moore’s law (device dimension scaling leading to: performance enhancement, higher transistor count per chip area, and reduced transistor cost) is running out of steam. Parasitic phenomena - such as: short channel effects, gate leakage, device-to-device variability - impact the device functionality. Nevertheless, several radical innovations in the recent years have allowed to continue the unabated performance enhancement, overcoming the challenges associated with further scaling of the device dimensions. Novel device engineering techniques (e.g., channel strain), materials (e.g., high-k dielectrics, high mobility channels) and device architectures (e.g., FinFETs) have been introduced.
In order to continue increasing the circuit functionality per area, a novel concept has been envisioned which consists of stacking transistors on top of each other sequentially in the same front-end process flow (“3D Sequential Integration”). This approach would enhance device density per chip area, without requiring further reduction of the device dimensions. Additional potential advantages include a simplified co-integration of heterogeneous devices technologies (e.g., Si and Ge/IIIV channel FETs; logic and optical devices) and a reduction of the length of interconnection lines, with the associated beneficial reduction of signal propagation delays.
The most crucial challenge of 3D Sequential Integration is the management of process thermal budget. In standard CMOS technology, the thermal budget for the fabrication of a transistor typically exceeds 1000°C. This is to ensure device performance (activation of channel doping, formation of low resistance semiconductor-metal contacts), but also to cure defects in the high-k dielectric and improve the device electrical stability and reliability. However, such high temperature steps cannot be used in the fabrication of the top layer transistors as they would impact the integrity of the metal lines already in place in the bottom layer. Therefore, novel low temperature transistor fabrication processes need to be developed.
This PhD research will focus on overcoming the gate stack challenges associated with the thermal budget constraints of a 3D Sequential Integration. These challenges are twofold: on one hand, a sufficiently reliable high-k dielectric stack needs to be developed for the top layer without resorting to high temperature steps for defect curing. On the other hand, due to the limitations on the process temperature, doping activation and contact formation in the top transistor might need to be achieved with longer thermal steps, which might in turn affect the reliability of the bottom transistor (e.g., inducing undesirable diffusion of dopant atoms and other species present in the gate stack). As a consequence, the fabrication of the bottom devices might also need to be revised.
The daily work will involve electrical and physical characterization of fabricated test structures (MOS capacitors and transistors); interpretation of the experimental trends based on modeling and simulations; definition of experiments and feedback to device integration engineers, in iterative learning cycles.
Electronic engineering or physics (relevant courses: semiconductor physics, semiconductor devices, electrical measurements, chemistry for electronics)..
Type of work:
10% literature, 20% modeling and simulations, 70% experimental work.
Supervisor: Guido Groeseneken
Daily advisor: Jacopo Franco and Nadine Collaert
When you apply for this PhD project, mention the following reference code in the imec application form: ref. STS 1704-02.