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/Calendar/Essential verification with SystemVerilog

Essential verification with SystemVerilog

30 March - 03 April 2020 | imec, Leuven, BE

This event is cancelled.

Why participate

Get an in-depth introduction to verification methodologies through extensive features of SystemVerilog. This course further discusses the benefits of the SystemVerilog constructs and features, verification efficiency and productivity gain through this methodology. SystemVerilog verification features include abstract classes, constrained random stimulus, coverage, assertions, queues and dynamic arrays for an effective and efficient verification. This five-day course covers all the necessary basics of Systemverilog for verification, and targets an audience that wants to start using SystemVerilog for verification in their own designs.

After this course, the enlightened audience should be able to create their own verification scenario and also to implement it in an effective and reusable way.

Who should attend

Prerequisites for this course are being familiar with VHDL, Verilog, or C++. The minimal requirements for this course widely opens the door to a larger variety of audience. This course is aimed at high level designers of ASICS SoCs and systems in general, but also at managers to enhance their understanding of System to RTL level verification.

Bachelor and Master students are allowed when places available. No free registration.

Program overview

Day 1:

  • Verification intro
  • SystemVerilog basics (syntax, concepts, statements)
  • Scheduling
  • Testbench framework
  • Hands-on exercises

Day 2:

  • Advanced data types (arrays, queues)
  • Subroutines (functions, tasks)
  • Interfaces
  • Clock blocks
  • Hands-on exercises

Day 3:

  • Object oriented code, classes
  • Randomness
  • Constraints
  • Coverage and covergroups
  • Hands-on exercises

Day 4:

  • Semaphores, maiboxes
  • Assertions, sequences
  • Binding
  • Hands-on exercises

Day 5:

  • Transaction Level Modeling
  • Direct Programming Interface
  • Open Verification Library
  • UVM intro
  • Hands-on exercises

Lecturers

Marian Verhelst - KU Leuven
Nele Mentens - KU Leuven
Jo Vliegen - KU Leuven

Register

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