SPIE 2022
/SPIE Advanced Lithography + Patterning 2022

SPIE Advanced Lithography + Patterning 2022

24 - 28 April 2022 | San Jose (CA), USA

This year at SPIE Advanced Lithography and Patterning, imec presents no less than 31 papers and co-authors 20 papers, showing progresses for the next generation of patterning technologies. 12 of these papers relate to high-NA EUV lithography, which will be key to advance Moore’s Law beyond 2nm technology generations. In a press release on high-NA EUV lithography, imec will announce advances in developing patterning and etch processes, in screening new resist and underlayer materials, in improving metrology and in photomask technology.

At the plenary presentations, imec President and CEO Luc Van den hove gives a talk titled ‘The Endless Progression of Moore's Law’. John S. Petersen, Scientific Director at imec, will give a course on Stochastic Lithography.

Plenary presentation

The Endless Progression of Moore's Law by Luc Van den hove, President & CEO of imec

Today, we are at the dawn of the 5th disruptive innovation wave. This emerging fifth wave, the deeptech wave, builds on the convergence of technologies such as AI, material science, biology, semiconductors … to disrupt virtually every aspect of the physical world we live in.

Semiconductors will be the core of many deeptech innovations thanks to their massive integration power, accessible mass production and low cost. To enable these deeptech innovations, Moore’s law will have to continue to address insatiable demands for more computation and more storage. We will realize Moore’s law by a multitude of approaches: continue traditional scaling, new devices, new switches, leverage the use of the third dimension, and paradigm shifts on how to build future systems. The challenges to bring these innovations to the market are huge. Therefore, we will have to approach this evolution through a major ecosystem, bringing together the right companies, the right R&D resources, perform this in leading-edge infrastructure, with the right funding and government support.

Highlights

EUV low-n attenuated phase-shift mask on random logic Via single patterning at pitch 36nm, L. E. Tan et al.

Investigation of low-n mask in 0.33 NA EUV single patterning at pitch 28nm metal design, D. Xu et al.

Deep learning denoiser assisted framework for robust SEM contour extraction and analysis for advanced semiconductor node, B. Dey et al.

Deep Learning-based defect classification and detection in SEM images, B. Dey et al.

Metrology of thin resist for high NA EUVL, G. Lorusso et al.

Low-voltage aberration-corrected SEM metrology of thin resist for high-NA EUVL, M. Zidan et al.

Resist and reticle activities towards High-NA EUV ecosystem readiness, J. Santaclara (ASML Netherlands) et al. – co-authored by imec

Resist line edge roughness mitigation at high-NA EUVL, E. Ohtomi (Western Digital GK) et al. – co-authored by imec

Approaches to enable patterning of tight pitches towards High NA EUV, K. Tadatomo (Tokyo Electron Kyushu Ltd.) et al. – co-authored by imec

High throughput scanning probe metrology for high-NA EUV photoresist profiling, A. Khatchaturiants (Nearfield Instruments B.V.) et al. – co-authored by imec

Unbiased roughness measurement of thin resists, C. A. Mack (Fractilia, LLC) et al. – co-authored by imec

Courses

24 April, 2022, 8:30 AM

Stochastic Lithography by Chris A. Mack (Fractilia, LLC) and John S. Petersen (imec)

This course will look at how stochastic variation during lithography affects semiconductor devices, how to measure stochastic variations, the major causes of stochastic variation, and what stochastics will mean for the future of lithography scaling.

Papers

On demand

Challenges with SOT-MRAM integration towards N5 node and beyond, M.K. Gupta et al.

25 April, 2022

EUV based multi-patterning schemes for advanced DRAM nodes, S. Das et al.

To bake or not to bake... : the impact of prebake in the EUV resist process, I. Pollentier et al.

Spatial frequency breakdown of CD variation, T. Kovalevich et al.

26 April, 2022

A yield prediction model and cost of ownership for productivity enhancement beyond imec 5nm technology node, Y. Tsai et al.

Quantifying process parameter impact on edge placement error using machine learning based analytical engine, A. Oak et al.

Exploring the synergy between EUV lithography and directed self-assembly, H. S. Suh et al.

Design and mask optimization toward low dose EUV exposure, D. Xu et al.

Deep learning denoiser assisted framework for robust SEM contour extraction and analysis for advanced semiconductor node, B. Dey et al.

Adhesion and collapse of EUV photoresists and the role of underlayers, R. Fallica et al.

27 April, 2022

Design, patterning, and process integration overview for 2nm node, Y. Drissi et al.

Investigation of low-n mask in 0.33 NA EUV single patterning at pitch 28nm metal design, D. Xu et al.

EUV low-n attenuated phase-shift mask on random logic Via single patterning at pitch 36nm, L. E. Tan et al.

Deep learning-enabled vertical drift artefact correction for AFM images, D. Cerbu et al.

Metrology challenges in the era of high NA EUV, A. Niroomand et al.

Evaluation of Ta-Co alloys as novel high-k EUV mask absorber, D. Thakare et al.

Patterning of Ru metal lines at 18nm pitch, S. Decoster et al.

Outlier analysis for understanding process variations and probable defects, M. Gupta et al.

Deep Learning-based defect classification and detection in SEM images, B. Dey et al.

Regularized autoencoder for the analysis of multivariate metrology data, M. Saib et al.

Low-voltage aberration-corrected SEM metrology of thin resist for high-NA EUVL, M. Zidan et al.

Metrology of thin resist for high NA EUVL, G. Lorusso et al.

Patterning challenges and opportunities in nanosheet device architectures, N. Horiguchi et al.

Deep Learning based defect classification and detection in SEM images: A mask R-CNN approach, B. Dey et al.

Top-down spectroscopic techniques for fast characterization of nanosheet and forksheet devices, J. Bogdanowicz et al.

Tone reversal patterning for advanced technology nodes, F. Schleicher et al.

28 April, 2022

Orthogonal array pillar process development for high density 4F2 memory cells at 40nm pitch and beyond, M. Pak et al.

A lithographic and etching study on EUV contact hole patterning for stochastic process mitigation, D. De Simone et al.

Buried power rail integration for CMOS scaling beyond the 3 nm node, A. Gupta et al.

MOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT), Z. Tao et al.

Middle-of-line plasma dry etch challenges for buried power rail integration, D. Radisic et al.

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