Towards next-generation computing
imec - Leti Workshop@IEDM
December 8, 2019
Nikko Hotel, San Francisco
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Do you want to stay on top of next-generation computing?
Are you looking for an extensive overview of the challenges and solutions ahead?
Are you eager to connect with leading experts on technologies for artificial intelligence and quantum computing?
Be the first to discover groundbreaking results in nanoelectronics, micro- and digital tech during a workshop co-hosted by Leti and imec – two leading European research centers – on the eve of the 2019 IEEE International Electron Devices Meeting.
Our pre-IEDM 2019 workshop brings together global executives, top scientists and experts from imec and Leti. Strictly invitation-only, it will offer you strategic networking opportunities and a head-start towards next-generation computing.
Maximize your participation in IEDM 2019. Join imec and Leti at our workshop & networking event!
05:30 - 06:00: Welcome Coffee & Registration
06:00 - 06:10 : Welcome by the CEOs of imec and Leti - Luc Van den hove, President & CEO, imec and Emmanuel Sabonnadiere, CEO, Leti
06:10 - 06:30: Introduction: Computing for the Coming Superstorm of Abundant Data - Subhasish Mitra, Professor Dept. of Electrical Engineering and Dept. of Computer Science, Stanford University
06:30 - 06:50: Session 1 - Artificial intelligence
06:50 - 07:10: Session 2 - Quantum Computing
07:10 - 07:30: Conference highlights
07:30 - 07:35: Conclusion by the CEOs of imec and Leti - Luc Van den hove, President & CEO, imec and Emmanuel Sabonnadiere, CEO, Leti
07:35 - 09:00: Reception
The workshop is co-chaired by:
Since November 20th, 2017, Emmanuel Sabonnadiere has been CEO of Leti, institute of CEA-Tech. Before, he was in charge of the industrial partnerships of CEA Tech.
Previously, he was CEO of the Business Group Professional of Philips Lighting based in Amsterdam (NL). From 2008 till 2014, he was CEO & Chairman of General Cable Europe based in Barcelona (Spain). From 2005 till 2008, he was CEO of NKM Noell at Wurzburg (Germany). He has been vice-president of the Distribution Transformers division of Alstom T&D for 5 years. He began his career in 1992 with Schneider Electric holding various positions including that of Managing Director of development for equipment units. He has a strong technological background combined with a successful business track record over decades. With 25+ years of executive leadership of large operations, he produced successful operating results and great team building. He has gained a sound experience of change management in large multi-cultural matrix organizations in order to adapt to the new markets conditions and a strong knowledge of European and international environments. He designed and set-up strategic plans including innovation process. He believes in operational excellence, technology innovation, talent management and enthusiasm in leadership. He obtained a PhD in physics (France), and an engineering degree in Information Technology (France). He holds an MBA (France). He is a member of the Advisory Board of IAC.
Luc Van den hove is President and CEO of imec since Juli 1, 2009. Before he was executive vice president and chief operating officer. He joined imec in 1984, starting his research career in the field of silicide and interconnect technologies. In 1988, he became manager of imec’s micro-patterning group (lithography, dry etching); in 1996, department director of unit process step R&D; and in 1998, vice president of the silicon process and device technology division. In January 2007, he was appointed as imec's EVP & COO. Luc Van den hove received his PhD in electrical engineering from the KU Leuven, Belgium. He has authored or co-authored more than 200 publications and conference contributions.
Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University. He directs the Stanford Robust Systems Group, co-leads the Computation focus area of the Stanford SystemX Alliance, and is a faculty member of the Wu Tsai Neurosciences Institute. Prof. Mitra also holds the Carnot Chair of Excellence in NanoSystems at CEA-LETI in Grenoble, France. His research ranges across robust computing, NanoSystems, Electronic Design Automation, and neurosciences. Results from his research group have been widely deployed by industry and have inspired significant development efforts by government and research organizations in multiple countries.
Jointly with his students and collaborators, Prof. Mitra demonstrated the first carbon nanotube computer and the first three-dimensional NanoSystem with computation immersed in data storage. These demonstrations received wide-spread recognition: cover of NATURE, Research Highlight to the United States Congress by the National Science Foundation, and highlight as "important, scientific breakthrough" by news organizations around the world.
In the field of robust computing, Prof. Mitra and his students created key approaches for soft error resilience, circuit failure prediction, on-line self-test and diagnostics, and QED (Quick Error Detection) design verification and system validation. His earlier work on X-Compact test compression at Intel Corporation has proven essential to cost-effective manufacturing and high-quality testing of almost all electronic systems across the industry. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools.
Prof. Mitra's honors include the ACM SIGDA / IEEE CEDA Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation's Technical Excellence Award (for innovation that significantly enhances the semiconductor industry), the Intel Achievement Award (Intel’s highest corporate honor), and the United States Presidential Early Career Award for Scientists and Engineers from the White House. He and his students have published award-winning papers at major venues: ACM/IEEE Design Automation Conference, IEEE International Solid-State Circuits Conference, ACM/IEEE International Conference on Computer-Aided Design, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors "for being important to them during their time at Stanford."
Diederik Verkest holds a Ph.D. in Applied Sciences from the KU Leuven (Belgium). After working in the VLSI design methodology group of imec (Leuven, Belgium) in the domain of system-on-chip design, he joined imec’s process technology unit as director of imec's INSITE program focusing on co-optimization of design and process technology for sub-10nm nodes.
Dr. Alexandre Valentian received the M.S. degree and the PhD. degree in 2001 and 2005 respectively, both in electronic engineering. He joined CEA-LETI Laboratory in the Center for Innovation in Micro & Nanotechnology (MINATEC), Grenoble, France, in 2005. His research interests include technology-design co-optimization in FD-SOI technology, 3D monolithic technology and non-volatile memory technology. He is actively pursuing the design and implementation of Spiking Neural Networks exploitation RRAM technology.
Dr Valentian has authored and co-authored 13 journal papers and 60 publications in scientific conferences. He holds 4 patents.
Abstract: Technological solutions for improving the figures of merit of Edge AI applications
Edge AI applications are calling for specialized ASICs (Application Specific Integrated Circuits) and System-on-Chip accelerators, in order to strongly decrease the power dissipation figure. In the near future, those applications will be based on inference-only tasks: the neural network is learnt offline and the classification tasks run locally. However, as mundane as it might appear, this class of application already necessitates optimized architectures for (1) reducing data movement to a minimum and (2) exploiting sparsity of weights and activations. In the longer run, online learning will also be considered for Edge AI applications, e.g. for lifelong learning or adaptation purposes. However, online learning requires massive memories, for storing all the intermediate activation results (3).
In this presentation, technological solutions will be detailed to address these three challenges, which are today hampering the adoption of advanced Edge AI applications.
Dr. Maud Vinet (CEA-Leti, University Grenoble Alpes, France) is currently leading the quantum computing program in Leti. Together with Tristan Meunier (CNRS) and Silvano de Franceschi (Fundamental research division from CEA), they received an ERC Synergy grant in 2018 to develop silicon based quantum computer.
She defended a PhD of Physics from University of Grenoble Alps and was hired Leti in 2001 as a CMOS integration and device engineer. From 2009 to 2013, she spent 4 years with IBM to develop Fully Depleted SOI with IBM and STMicroelectronics. In 2015, she spent 6 month with GLOBALFOUNDRIES in Malta, NY to launch 22FDX program.
From 2013 to 2018, she managed the Advanced CMOS integration team activities in Leti (~50 people). In 2019, she was appointed project leader for the quantum computing program in Leti.
Maud Vinet authored or co-authored about 200 papers, she owns more than 70 patents related to nanotechnology and her Google h-index is 42.
Abstract: Si spin qubit challenges for large scale
Quantum computing is expected to extend the high performance computing roadmap at the condition of being able to operate a large number of qubits. Si-based QC appears as a promising approach to build a quantum processor; thanks to the size of the qubits, the quality of the quantum gates and the VLSI ability to fabricate billions of closely identical objects. The quality of Si spin qubits has improved very fast with the introduction of isotopically purified 28Si, as observed by multiple research groups.
In this presentation, we will discuss the architectures to design a large scale quantum computer based on Si spin qubits and we will review the hardware integration choices and the associated challenges both from technology and low level software perspectives.
Iuliana P. Radu is Director of Quantum and Exploratory Computing at imec. Her activities include work on beyond CMOS device concepts such as spintronic majority gates and wave computing and novel materials and their possible applications in the semiconductor industry. Quantum Computing includes work on qubit devices and the periphery circuits meant to control them. Prior to establishing the Beyond CMOS program at imec in 2013, she was a Marie Curie and FWO fellow at KU Leuven and imec. Her work encompassed devices using the metal to insulator transition, ionic and electronic transport in functional oxides, and devices with graphene and other 2D materials.
Iuliana has received a PhD in Physics from MIT in 2009 where she searched for Majorana fermions in the quest to build very reliable qubits for Quantum Computing. She has been an author on over 170 papers in leading peer-reviewed journals and conferences. She has given more than 40 invited talks at international conferences and seminars where she is a frequent speaker on quantum computing and exploratory devices for classical computing. Currently a sub-committee co-chair for IEDM, and program committee member for SISC and SNW.
Abstract: Disruption in Compute: Building the Quantum Computer in a 300mm Fab
For many decades, transistor scaling trends have followed Moore’s law. Many in the industry predict that this trend will hit a roadblock in the near future as the costs, process complexity and even fundamental limiters continue to accumulate. However, the need for increased computing performance is real and must be fulfilled. Quantum computing promises to be the biggest disruptive method to deliver the performance increase in computing (even if only for specific classes of task).
Building a quantum computer is a might task and cooperation is key to bringing to realization. In this talk, we will outline how imec is working to enable the technologies needed for quantum computing. We are taking a broad systems perspective to find the path towards up-scalability and increasing the number of qubits. The focus is on two types of qubits (spin qubits in Si and superconducting qubits) which show high potential towards large scale integration. Imec is fabricating these qubits in its state-of-the-art 300mm fab using the know-how and mindset developed for advanced CMOS scaling. Collaborations are already in place and more being set-up to characterize these devices and operate for quantum computing. The quantum computer will require a lot more that just qubits as it is expected that the circuitry to control these qubits will require a lot more power and space than the qubits themselves. Imec is also working on the cryo-electronics needed for the quantum computer and we will describe some of the activities in this presentation.
Julien Arcamone is currently the Head of the Microelectronics Components Department, within CEA-Leti’s Silicon Components Division.
He graduated from INSA Lyon in Materials Engineering in 2003. Then, he received a PhD in Electronic Engineering in 2007 from CNM-IMB (CSIC) and the Autonomous University of Barcelona (Spain), and the HDR from Grenoble-Alpes University in 2017. From 2008 to 2012, he was a staff research scientist in the Micro and Nanosystems group at CEA-Leti. His research area was involving the design of MEMS and NEMS devices for advanced sensing and actuating applications, as well as the integration of Nano mechanical devices with CMOS circuitry.
He was a member of IEEE MEMS conference’s TPC in 2016 and 2017. Dr. Arcamone has authored or co-authored more than 75 peer-reviewed scientific publications and 1 book, and is the co-inventor of 9 patents.
In 2012, he took over responsibility of Business Development and industrial collaborations of Leti’s MEMS activities: in this frame, he has been launching various bilateral collaboration programs with major MEMS companies worldwide. In January 2018, he was appointed Leti Executive Vice-President of Business Development: at this position, he has been building partnerships with major companies worldwide, with a focus on Asia, in the field of Semiconductor Technologies. In September 2019, he was appointed Head of the Microelectronics Components Department of CEA-Leti’s Silicon Components Division, whereby he manages all Leti teams (process integration, device, simulation & characterization) dedicated to Advanced CMOS and memories.
Serge Biesemans holds a Masters degrees in Electrical Engineering and Physics from KU Leuven University, Belgium. He started in 1992 his PhD researching sub-100nm gate MOSFETs. He started his career in 1998 at IBM development in NY working on 0.18 and 0.13µm technologies. In 2002, he started as director of Device and FEOL integration at imec. He held several management responsibilities, including helping to shape the imec IIAP core program as well as the specialty components program. In 2012, Serge joined Tokyo Electron (TEL) as European VP of Technology Marketing supporting 3 equipment factories with the research capabilities of imec. In 2019, Serge returned to imec supporting all semiconductor research programs.
Prof. Dr. Stefan De Gendt obtained the PhD degree in Science, Chemistry from the
University of Antwerp in 1995. Since then, he has been working at imec in a wide range of material and process related domains. His research topics include cleaning and surface preparation processes, high-k and gate metal materials as well as the exploration of 0D to 2D materials for technology applications.
He currently holds a position of scientific director and group leader, responsible for exploring new materials and processes in the Advanced Patterning, Process & Materials department at imec. Since 2003 he is associated to the Katholieke Universiteit Leuven (KULeuven) as a part-time full professor. He has (co-)authored more than 400 technical papers in refereed journals and is (co-)inventor of several patent applications.
He has been actively involved in the organization of IEDM and is currently serving as Senior Vice President of the Electrochemical Society.
Thomas Ernst is chief scientist and VP research at CEA- Leti with responsibility for long term research strategy and partnerships.
He received his Electronics Engineering degree, Ph.D. and accreditation for PhD supervision from National Polytechnics Institute of Grenoble (France) in the field of electronics and microelectronics.
From 1997 to 2000, he developed advanced SOI CMOS characterisation, physical modelling and circuit-level performance evaluation with STMicroelectronics and CNRS.
He then joined CEA-Leti were he led different research projects with industry including SOITEC, STMicroelectronics, IBM, Freescale, NXP, and also a start-up on gas sensing (APIX). He led the team developing the first CMOS 3D-stacked nanowires. Dr. Ernst is author or co-author of over 180 technical journal papers and communications at international conferences. He is author or co-author of 20 patents. He is or was a member of committees of VLSI technology symposium, IEDM, ESSDERC, ULIS, ICICDT, DATE conferences, IEEE EDS France (secretary). He was a recipient of research grant from the European Research Council (ERC) to develop multi-physics integrated smart systems for sensing application.
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VP Corporate International Relations
International Leti Press Communication Representative
Imec is a world-leading R&D and innovation hub for nanoelectronics and digital technology. We leverage the expertise of nearly 4,000 top scientists and engineers, and our global ecosystem of partners across a multitude of industries, to push the boundaries of IC technology and create groundbreaking innovation in application domains such as healthcare, smart cities and mobility, logistics and manufacturing, energy and education.
Leti, a technology research institute at CEA Tech, pioneers micro- and nanotechnologies, tailoring differentiating applicative solutions that ensure competitiveness in a wide range of markets. The institute tackles critical challenges in health care, energy, transport, and ICTs. Its multidisciplinary teams deliver solid expertise for applications ranging from sensors to data processing and computing solutions, leveraging world-class pre-industrialization facilities. CEA-Leti builds long-term relationships with its industrial partners – global companies, SMEs, and startups – and actively supports the launching of technology startups.