New materials as a fundamental enablers of next-generation logic and memory devices
Memory and logic device scaling has continued to make impressive progress in the past decades. This progress has not only been driven by continued dimensional scaling, but equally by the development of new device concepts such as finFET or nanosheet, as well the introduction of functional and sacrificial materials. In logic, plenty of examples can be identified transitioning through the different technology nodes, patterning materials like photoresists and hard masks, but also functional materials such as high-dielectric constant oxides contacted with a metal gate, low-k spacers, silicon germanium channels, lower resistance metals and low-dielectric constant oxides in the back end of line. Memory has been driven by material innovation in a variety of applications such as DRAM, flash or storage class memories, using charge storage, phase change and magnetic type materials.
As we move forward, the importance of enabling new material only grows, as do the challenges associated with their introduction. To accelerate new material development, imec has developed a unique infrastructure, linking virtual materials exploration via simulation to rapid lab screening and characterization in relevant on-scale devices in our 300mm fab. This flow enables not just a rapid identification and assessment of new materials, but also the development of key processes, such as etch and cleaning, required for their integration into a device. These new processes can then be efficiently introduced to the industry through our extensive partnerships with materials and equipment suppliers.
In this talk we will explore imec’s vision for material development and integration into tomorrow’s logic and memory products.
About Steven Scheer
Steven Scheer has been the Vice President of Advanced Patterning Process and Materials (APPM) at imec since January 2019. His responsibilities include patterning, unit process and new materials development for logic, memory, photonics, and 3D integration. Prior to that, he was an account technology director with Tokyo Electron Ltd. (TEL), responsible for customers in the Portland OR area. He worked at TEL for 13 years where he was responsible for R&D in patterning and cleans, including management roles in the US as well as at TEL’s factory in Kumamoto Japan and with the corporate R&D organization in Tokyo. He began his research career at IBM in Fishkill NY, working on 90 and 65 nm patterning development. He holds a Ph.D. in Chemical Engineering from the University of Texas at Austin.
