3D System Partition Aware Cache Design

The impressive growth of the semiconductor industry in the past few decades has been driven by CMOS technology scaling. Miniaturizing the CMOS devices improves integration density, logic performance while lowers the power consumption. Embedded cache size and performance are also increased dramatically over the years and thereby the performance of the system of the chip (SoC). However, beyond 10nm node, the scaling of Static Random-Access Memory (SRAM) becomes increasingly difficult. Furthermore, the resistance of local interconnect in advanced nodes severely degrades the performance of SRAM. Achieving power, performance, and area gain from CMOS technology scaling as predicted by Moore’s law thus requires innovation in technology, device architecture, circuit, and system design. Three-dimensional (3D) integration has been perceived as the promising candidate for extending Moore’s law without scaling the critical device/interconnect dimensions. 3D integration offers additional freedom in designing and optimizing the SRAM transistors and interconnects separately than the classical planner 2D ICs. 3D integration thus offers the opportunity to improve system performance and lower power consumption. Furthermore, in a 3D system, SRAM cache can be easily replaced by novel non-volatile memories such as MRAM, SOT-MRAM. Thereby a dramatic reduction in cache power consumption is expected.

In modern mobile and high-performance processors larger caches (L2 and on) are assembled from smaller memory macros (typically <64kB) to minimize internal macro delays. In 2D, such configurations will result in long wires required to route all macros, adding interconnect delays to memory access time and aggravating the memory wall. 3D integration technologies can address this problem by making logic to memory connections shorter with Memory-on-Logic 3D-ICs. Further, 3D integration adds extra optimization possibilities for memory macros: when implementing 3D Memory-on-Logic systems by partitioning memory macros (L2) from the logic core, the macro layout can be optimized by moving all the pins from the edge to the centre of the macro, allowing address and IO pins BEOL routing inside a macro to be reduced. Both SRAM macro performance and power efficiency are improved as a result. Face-to-Face (F2F) and Wafer-to-Wafer (W2W) hybrid bonding at sub 1um pitch have been demonstrated by imec which provides fine pitch 3D connections between memory macro die and logic die. This is also the key enabler of memory on logic integration at advanced technology nodes such as 3nm, 2nm and beyond. The cache optimization in a 3D system is however not straight forward. The signal and power pin for memory macro in a 3D SoC could potentially create congestions.