/3D System Partition Aware Cache Design

3D System Partition Aware Cache Design

Leuven | More than two weeks ago

Energy efficient memory for high performance computes

The impressive growth of the semiconductor industry in the past few decades has been driven by the CMOS technology scaling. Miniaturizing the CMOS devices improves integration density, logic performance while lowering the power consumption. Embedded cache size and performance also increase dramatically over the years and thereby the performance of the system of the chip (SoC). However, beyond the 10nm node, the scaling of Static Random-Access Memory (SRAM) becomes increasingly difficult. Furthermore, the resistance of local interconnect in advanced nodes severely degrades the performance of SRAM. Achieving power, performance, and area gain from CMOS technology scaling as predicted by Moore’s law thus requires innovation in technology, device architecture, circuit, and system design. Three-dimensional (3D) integration has been perceived as a promising candidate for extending Moore’s law without scaling the critical device/interconnect dimensions. 3D integration offers additional freedom in designing and optimizing the SRAM transistors and interconnects separately than the classical planner 2D ICs. 3D integration thus offers the opportunity to improve system performance and lower power consumption. Furthermore, in a 3D system, the SRAM cache can be easily replaced by novel non-volatile memories such as MRAM, SOT-MRAM. Thereby a dramatic reduction in cache power consumption is expected. The cache optimization in a 3D system does not state forward. The signal and power pin for memory macro in a 3D SoC could potentially create congestion.

In this work, the candidate will interact with different imec groups working on technology development, material selection, TCAD simulation, compact modelling, and circuit design to identify the challenges and opportunities of cache design for the 3D systems. The primary objectives are to come up with memory bit-cell architecture, array design, read/write assist circuit design, and efficient interconnect architecture to support 3D system design. The system/circuit architectures used in the work will drive the imec logic and memory technology roadmap.

Type of project: Combination of internship and thesis, Thesis

Required degree: Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Shairfe Muhammad Salahuddin (Shairfe.Muhammad.Salahuddin@imec.be)