Emerging applications like Internet-of-Things (IoT) and 5G will require the enablement of a variety of functionalities. There is more and more a need for hybrid scaling where different technologies blend together, leveraging new materials and devices, to enhance and optimize the overall system. Co-integration either on the same substrate or through 3D stacking will be key enablers for these heterogeneous systems. In that context, IIIV materials, with their high electron mobility and low band gap, are attractive candidates for high speed, low power and optical applications. Devices such as HEMT, HBT, TFET, lasers are quite dissimilar in nature to the standard CMOS technology. With the need to integrate them on a common Si platform, challenges in power reduction, performance improvement and area efficiency become very prominent. Especially parasitic reduction (resistance and capacitance) will be key to enable these technologies. While so far these devices were fabricated on small sized substrates using lab-like processing, Si p-line compatible materials will need to be considered to upscale them to a 300mm platform. Therefore, careful material exploration and design is mandatory.
The purpose of this PhD is to explore the effects of material parameters such as doping and crystal defects, in parallel with device design and selective area epitaxy requirements.
The daily activities will include fabrication of devices and test structures in IMEC’s clean room lab environment; electrical and physical characterization; interpretation of experimental results based on modeling and simulations; definition of experiments and reporting.
Required background: Nanotechnology, Electronics, Materials science, IIIV materials
Type of work: 80% experimental work, 10% literature study, 10% modeling
Supervisor: Marc Heyns
Daily advisors: Tsvetan Ivanov, Bernardette Kunert
The reference code for this PhD position is STS1712-01. Mention this reference code on your application form.