During the last decades, an enormous growth of applications in the field of information, telecommunication and life sciences has occurred. To sustain this growth, the amount of integrated circuits (IC) in our daily life is augmenting, ranging from computers, tablets, mobile phones, TV’s to cars, smart glasses and healthcare. Innovations in electronics do not only increase computing power and memory, but also make our devices more energy-efficient by reducing the power consumption. Such innovations are being enabled by miniaturization of the device dimensions, by the introduction of new materials with enhanced properties, and by introducing new device architectures and concepts, often implying an evolution towards three dimensional structures. For example, in 1971, the most advanced processors held 2300 transistors; in 2017, processors with 14 nm technology hold over 3 billion transistors. This evolution is bringing many challenges to the integration processes involved in the manufacturing of nano-electronic devices. As the device dimensions decrease, the combination of the conventional “top-down” patterning techniques with alternative “bottom-up” strategies is becoming more and more attractive. Examples include self-aligned multiple patterning, directed self-assembly (DSA) and area selective deposition. In area selective deposition, differences in surface reactivity are exploited to deposit material according to certain predefined patterns, while other patterns on the same substrate remain unaffected. This selectivity can be achieved by processes that are based on surface reactions between gas phase precursors and the specific pattern, as used in chemical vapor deposition (CVD) and atomic layer deposition (ALD). As such, area selective deposition is of high interest as it could be used as a bottom up approach for patterning and to simplify integration flows or gain in integration margin. Area selective deposition could significantly reduce the ecological footprint of nano-electronic device manufacturing.
However, practical applications of area selective deposition today are still limited, mainly because selectivity has been demonstrated only for a limited number of materials. In addition, the inherent surface dependence of ALD and CVD processes is rarely sufficient, and a much higher selectivity is needed to enable applications in nano-electronic device fabrication. A better understanding on the role of the precursor of ALD and CVD processes is essential to expand the material combinations accessible by area selective deposition as well as to improve selectivity.
The general aim of this PhD project is to generate insight in suitable chemistries for area selective ALD and CVD processes. We will focus on area selective deposition of oxides and metals in view of their high potential for application in patterning. The impact of the precursor (size, polarity, reactivity ...), co-reagent and process conditions and how these affects selectivity need to be better understood, so that the process window for selective deposition can be broadened to enable applications in nano-electronic device manufacturing. For different precursors/processes, we will determine the selectivity window and investigate the nucleation mechanisms on the “growth” and “non-growth” surfaces. The latter is also of particular importance as insight in the mechanisms for selectivity loss can be used to design selective deposition processes with improved selectivity. Both inherent selectivity and selectivity induced by surface passivation can be investigated. The research will be mainly experimental, but depending on the interest of the student a combined experimental/theoretical investigation might be possible. Second, this insight will be applied to design area selective deposition processes for relevant applications in nano-electronic device manufacturing. In our research program on area selective deposition, we leverage Imec’s 300mm production line and advanced node technologies to gain access to patterned structures with dimensions down to tens of nanometers in order to industrially relevant research of area selective deposition. This enables the investigation of the impact of the integration process on surfaces, as well as to address additional questions such as how to maintain lateral confinement.
Required background: chemistry, materials, nanotechnology
Type of work: 10% literature study, 90% experimental work (depending on the interest of the student a combined experimental/theoretical investigation might also be possible)
Supervisor: Annelies Delabie
Daily advisor: Annelies Delabie
The reference code for this PhD position is STS1712-36. Mention this reference code on your application form.