The number of neural-interface channels is continuously increasing to improve the quality of the neural recording/stimulation. A high data rate RF transceiver as a wireless interface for such devices can improve the comfort level of the patients/animals, and at the same time minimize the risk of infection. To support up to few hundreds or even thousands channels of neural signal recording/stimulation, this RF transceiver should have be capable of providing a throughput up to few tens or even hundreds Mbps without any compression. However, due to the limited energy source available inside the body, e.g., through RF powering, the DC power consumption of such high throughput RF transceivers need to be lower than few mW.
In this PhD project, an implantable low-power high-data-rate CMOS RF transceiver for neural-recording/stimulation applications will be developed, and it will be also be validated together with imec neural-recording experts using the in-house neural interface.
Required background: Solid background in RF and analog integrated circuit design, preferably with sufficient experience in tape-out (in e.g., 40nm) and lab evaluation
Type of work: RF architecture innovation, RF integrated circuit design, co-develop system demonstrator
Supervisor: Piet Wambacq
Daily advisors: Yao-Hong Liu, Marco Ballini
The reference code for this PhD position is SE1712-05. Mention this reference code on your application form.