The electrical breakdown of dielectric materials is a widely studied phenomenon in the semiconductor industry. The first dielectric breakdown studies were performed in the 50’s after the invention of silicon-based transistors. For many decades, the focus was mainly on gate dielectrics, as the interconnect dielectric was simply not a reliability concern, due to the excellent breakdown strength of the silicon dioxide (SiO2) that was used to isolate the lines.
It is only 10-15y ago, with the introduction of carbon-doped (porous) oxides, intended to lower interconnect capacitances, that the breakdown of the interconnect dielectric became a reliability concern. Nowadays the breakdown of the interconnect dielectric is a heavily studied phenomenon, as it is considered a potential showstopper for further interconnect scaling.
On the one hand, advanced patterning options, such as self-aligned quadruple patterning (SAQP), extreme ultra-violet (EUV) lithography, fully self-aligned via’s (fSAV), super via’s etc. will enable further scaling of the interconnect dimensions below 42nm pitch. On the other hand, they will introduce additional variability, that is larger deviations from the intended (ideal) interconnect patterns. Examples of variability are line-edge-roughness (interconnect lines are not perfectly straight, but present a certain degree of roughness), via-misplacement (lines from different metal levels are connected through via’s and these via’s do not perfectly land on the connected lines) and CD-variation (line width and line-to-line spacing vary from die to die within the wafer). Dielectric breakdown is strongly affected by such variability, which deteriorates the reliability margin with respect to a “perfectly” fabricated interconnect. A proper understanding of the impact of variability on dielectric reliability is key for realistic reliability predictions.
During this PhD, models will be developed to deal with variability in a way that is statistically correct. The following challenges need to be addressed. First, a methodology needs to be put in place for the accurate determination of the electrical field between wires at very small interconnect spacing (below 5nm). Second, statistical models describing the effect of variability on lifetime distributions and acceleration models need to be built. A further refinement of the model could include the impact of dielectric degradation during processing; for example, the increase of defect density in the dielectric reduce the breakdown strength of the material, thus adds on top of the field enhancement. The final goal of this PhD is to build a general model that, once calibrated to actual dielectric breakdown data from current technology, will allow predicting the reliability margin of future technology generations with scaled interconnect dimensions.
Required background: Given the highly statistical and mathematical content of this PhD program, a candidate with a master in this field or with a strong interest in statistics/mathematics is preferred.
Type of work: 10% close literature follow-up, 30% electric field simulations, 30% statistical models,30% experimental validation/calibration of models
Supervisor: Ingrid De Wolf
Daily advisor: Ivan Ciofi
The reference code for this PhD position is STS1712-11. Mention this reference code on your application form.