As a consequence of our increasing reliance on information nowadays, both for home and personal use along with business and professional needs, more and more data is being generated, processed, moved, stored, and retained in multiple copies for longer periods of time. Research has shown that the biggest performance bottleneck with popular smart-phone apps such as Facebook and Google Maps is, in fact, how fast they can read and write a device’s data storage. This suggests that without solving the ‘Memory Bottleneck’, the benefits of new networks and processors will be limited. Aggressive technology scaling has also, placed limitations on current memory and data storage technologies like SRAM, DRAM and Flash.
Thus, several new Non Volatile Memory (NVM) technologies are currently being investigated to eventually satisfy the need for continuously higher storage capacity and system performance, lower power consumption, smaller form factor, lower system costs and long data‐retention capability. Resistive RAM (RRAM), Phase Change RAM (PC-RAM) and Magneto-Resistive RAM (MRAM) are among the more mature NVM technologies. Spin Orbit Torque MRAM, Domain Wall Memory, Conductive Bridge RAM etc are some of the more recent NVMs with interesting characteristics. However, naively replacing the whole memory hierarchy with NVRAM is not a good idea. Each technology comes with a set of inherent flaws, like write endurance limitation, or high access latency, etc. To mitigate this problem, the memory system architecture of the system-on-chip should combine several regions of memory with different characteristics.
Research Target: Several concepts of non-volatile memories like ferro-electric, charge-storage, or resistive switching are being investigated at imec as potential candidates for both embedded and storage class domains. In this PhD thesis, the different technologies will first be compared and evaluated from a system perspective for the targeted platforms and application domains. The major part of this would involve circuit design and analysis of the device, selector and array to enable the NVM memory architecture. Another important aspect of the PhD work will be to evaluate the NVMs at the system level and characterize them with respect to performance requirements, block level definition, workloads and other key features. In order to realize this, a close interaction between circuit and system experts will be required.
Type of work: 45% circuit design, 30% system evaluation, 15% software, 10% literature
Supervisor: Francky Catthoor
Co-Supervisor: Jan Van Houdt
Daily advisor: Sushil Sakhare
The reference code for this PhD position is STS1712-33. Mention this reference code on your application form.