The most advanced commercial CMOS technologies rely heavily on mechanical stress to stretch out or compress silicon channels, leading in turn to increased mobility and performance. Since 2004, many stress techniques have been developed and studied such as virtual buffers, source/drain stressors and stressed contact etch-stop layers. Besides generating stress in the transistor channel, other considerations play a role to make stress techniques manufacturable. These considerations are mainly related to the risk of introducing defects and additional leakage, process controllability and introduction of additional parasitic resistances.
While stress techniques are well established for traditional planar and FinFET technologies, there are several alternative device architectures that have channels in the shape of a nanowire, or that rely on different processing schemes and crystallographic orientations of the channels. For these devices, plenty of research is needed to understand how stressors work and can be optimized. Furthermore, alternative semiconductor materials are being considered as transistor channel, such as germanium and III/V semiconductors, for which channel stress can also be desirable. Finally, at the nanometer scale the traditionally known stress effects on mobility and performance are invalid, as quantum effects like energy quantization and high-field, ballistic transport become more dominant. The purpose of this PhD is to simulate and study how stressors can be used most efficiently in the advanced MOS technologies mentioned above, and to validate the models with experimental results of mechanical and electrical properties.
Required background: electrical or materials engineering
Type of work: 25% literature, 50% TCAD, 25% experimental validation
Supervisor: Ingrid De Wolf
Daily advisor: Geert Eneman
The reference code for this PhD position is STS1712-29. Mention this reference code on your application form.