Thanks to technological advancements, high-quality healthcare devices, rivalling clinical level of accuracy have found their way into various wearable form factors. Imec has developed in the past numerous ASICs for both wearable and implantable healthcare. Examples include ASICs for electrocardiogram (ECG), electroencephalogram (EEG), bio-tissue impedance spectroscopy (BioZ), neural recording (AAP, LFP), ... Traditionally the main focus has been on improving the power and noise performance of the analog front-end circuits which largely determine the quality of recording. Since most biomedical signals are fairly low frequency, most designs use older technology nodes (like 180nm because of its excellent analog characteristics, mature simulation models and reasonable silicon cost). However as the applications these devices end up in become more advanced, there is a clear need to include ever more digital signal processing and wireless links on the chips. Unfortunately, these older technology nodes are not well suited for digital and RF functionality in a power- and area-efficient manner. While moving towards a more advanced CMOS node, like 40nm or 28nm, will obviously benefit digital and RF, these nodes are not very well suited for power-efficient high-precision analog due to the lower intrinsic gain, higher noise (due to gate leakage) and for analog circuits the area doesn’t scale as easily.
In order to leverage the scaling benefits, a paradigm shift is required for the analog front-end circuit design. Instead of using regular voltage-based circuits (i.e. instrumentation amplifiers, buffers, ADCs) people have started implementing time-based analog building blocks. This is an interesting approach which could leverage indeed the benefits of scaled technology nodes. Because the analog signal of interest is transformed into a time-based signal (frequency, phase, time, ...), it is also interesting to explore scalable performance architectures. Indeed, scalable performance could be achieved by modifying the clock at which these time-based circuits operate, trading time-resolution (and hence power) for performance (dynamic range). Such an approach is quite interesting to develop readout circuits that can be adapted to various applications. However, one could take this even a step further and look into adaptable performance analog front-ends. By adaptively scaling the performance on the fly, such circuits can adapt their noise, power and dynamic range to suit exactly the input signal. Because, especially in ambulatory (wearable) health care, the dynamic range of the input signal can change dramatically depending on external factors (such as the amount of motion), circuits are generally designed for worst case scenarios. This essentially means that most existing circuits consume much more power than needed. An adaptable performance analog front-end would provide a means to drastically reduce the power consumption in such cases.
This doctoral research will focus on scalable (and ultimately adaptable) performance analog front-end circuits for biomedical applications (i.e. ECG). The student will explore new readout architectures suitable for scaled technology nodes. The student will then design and implement these architectures in an ASIC. The student will be able to confirm their designs in realistic scenario’s.
Required background: electrical engineer with a strong affinity for analog integrated circuit design
Type of work: 70% analog circuit design, 10% system design, 20% measurements and validation
Supervisor: Chris Van Hoof
Daily advisor: Marco Ballini
The reference code for this PhD position is SE1712-13. Mention this reference code on your application form.