These last years, the demand for high-density and fast-access non-volatile memories has been steadily increasing. However, there is no existing product satisfying this need today, between the fast but volatile DRAM technology and the high-density but slow-access 3D Flash technology. Hence, the ‘Storage Class Memory’ (SCM) has emerged to fill this speed-density gap in the memory hierarchy, enabling the development of future computing and/or storage systems by providing a fast and cheap memory alternative.
Several emerging memory concepts, like resistive random-access-memory (RRAM), phase-change RAM (PCRAM), or Magnetic RAM (MRAM) concepts hold the promise of showing both speed and density specifications of SCM. On the other hand, in today’s memory array cross-point architecture, the main factor limiting high-density integration is the “sneak path” current or capacitive issue during read and write programming of the memory device. To overcome this issue a two-terminal access device (selector) in series with the memory element is required to enable addressing individual memory cells in an array without disturbing the others. This select device must be scalable, have high rectification ability, following the operation mode of the memory cell (typically bipolar) and allow for high drive current densities, required to switch the memory element.
To fulfill these requirements, many selector concepts are currently under investigation. Between them, imec has recently started the development of the Ovonic Threshold Switch (OTS) technology, relying on the abrupt current surge through a chalcogenide layer submitted to a threshold voltage. Although excellent potential was demonstrated for this technology [1,2], the switch mechanism is not well understood.
The purpose of this PhD is to investigate thoroughly the electrical properties of OTS devices, study the roles of composition, material variations, and integration processes on device parameters, in order to identify knobs allowing to improve the device towards SCM specs. Advanced processes will also be used to fabricate full one-selector one-resistor (1S1R) memory cells, either isolated or in test arrays, to enable in-depth exploration of the memory performance, as well as selector-resistive switching element compatibility and performance trade-offs.
In addition, a large part of the PhD work will be to develop a physics-based switching model, which should help complement compact, parametric models used at circuit simulation level, in order to enable assessment of the array performance. Overall, an important output of the PhD will be to establish the intrinsic limitations and potentials of the technology. Finally, the PhD work should not limit to OTS but should open to alternative and novel selector concepts showing potential for SCM. These may include for example diode concepts, MIEC (Mixed Ionic Electronic Conductor), or MIT (Metal-Insulator Transition) concepts.
The PhD work will be carried out in the frame of the Imec Industrial Affiliation Program (IIAP), thus in close relation with industrial partners and within a team consisting of experts in various fields (processing, integration, physical characterization, modeling, reliability...).
References:  B. Govoreanu et al., VLSI 2017,  S. Clima et al., IEDM 2017.
Required background: materials and device physics, electrical engineering.
Type of work: experimental work (10% lab fabrication and 40% electrical characterization), 30% physics-based modeling, 20% up-to-date literature on selectors
Supervisors: Ludovic Goux, Jan Van Houdt
Daily advisor: Ludovic Goux
The reference code for this PhD position is STS1712-07. Mention this reference code on your application form.