Active backside devices for CMOS technologies

The introduction of a backside power delivery network drastically improves the power and performance of an IC design. However, it also allows new opportunities for further improvements. Due to the wide free area on the backside, active devices could be added to optimize power/performance and/or functionality. In this work, we want to analyse the feasibility of such concept by considering a selection of the best candidate materials for active backside devices, as well as the area requirements and implications on the power delivery network.