/AI/ML-driven design space exploration for system-level optimization with emerging semiconductor technologies

AI/ML-driven design space exploration for system-level optimization with emerging semiconductor technologies

Internship/thesis - Leuven | More than two weeks ago

Using AI/ML for traversing the semiconductor technology innovation space  

With the rising use of machine learning in almost every application domain, there are increasing computational demands on electronic systems at every scale of computing. However, the deployment scenarios of each system limit the scalability of computing resources for different systems to varying extents. Traditional approaches to the related DSE problem have focussed on software and architectural degrees of freedom (DoFs). However, such limited DoFs also lead to limited system-level optimizations. To this end, emerging semiconductor technology innovations, both at the device- and integration-level need to be included in the DSE framework. The resulting design space is too large to be explored efficiently using traditional optimization methods. AI/ML-based methods such as regression-based predictions, knowledge discovery, etc. can help in traversing this large design space effectively.
 
The student will be working on developing DSE frameworks leveraging both emerging AI methods and state-of-the-art system-level characterization tools.

Type of work: 20% literature survey to gain an understanding of the landscape of technology innovations and stat-of-the-art reconfigurable technologies. 80% hands-on modelling and framework development for using system-level characterization tools along with AI/ML workflows.

Duration: 3-6 months

Required background: Implementing state-of-the-art AI methods using Python/C++. Knowledge of computer architecture/electronic systems is added benefit.

Bachelor's program: Computer Science, Engineering Technology 

Language requirements: English 

Type of Project: Combination of internship and thesis; Internship 

For more information or application, please contact Siva Satyendra Sahoo (siva.satyendra.sahoo@imec.be

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