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/Job opportunities/Algorithms for Hardware aware Neural Architecture Optimization

Algorithms for Hardware aware Neural Architecture Optimization

PhD - Leuven | More than two weeks ago

Design novel algorithms that optimize the structure of neural networks models to run on custom hardware.

Recent years have seen an explosion in the popularity of deep learning. Deep learning has been the focus of machine learning research as well as a key component in novel industrial applications.  The resulting neural networks  have achieved state-of-the-art performance in applications as diverse as computer vision, natural language processing , computer games and autonomous driving. These successes have led to the implementation of ever larger neural network models, requiring more and more compute and energy not only to train, but also to run.

The growing demand for efficient compute has spawned an array of new hardware accelerators for deep neural networks. These accelerators offer the possibility of providing more compute at a lower energy cost.  Being able to deploy deep models on these devices is an important goal, both to  enable the use of neural networks on devices with limited power, and to address environmental concerns regarding the energy consumption involved in deep learning.  However, running networks on accelerators often requires changes at the algorithmic level. Common requirements to transfer networks to hardware are to train low-precision quantized networks and to retrain networks to increase robustness to noise. These methods allow the transfer of many commonly used network architectures to novel hardware devices with minimal loss of performance. 

While it is possible to transfer common software neural network models to custom hardware, the current network architectures are developed for general purpose CPU/s/GPUs. This means that they are generally not optimized to make the best use of specific hardware devices. To maximize the efficiency of  hardware deployed neural networks, both hardware and neural network architectures need to evolve and adapt to each other. Adapting the network architectures to hardware requirements is currently a largely manual process. This process needs to consider multiple concerns like accuracy, energy consumption, hardware utilization, latency and others.  In order to drive further progress, there is a clear need to automate this complex process.

In the research community there has been a  growing interest in learning methods that automate the design of neural networks architectures. Algorithms based on distillation, network pruning and architecture search can design application specific neural network models that outperform hand-designed networks. The focus of this PhD will be the development of novel architecture optimization algorithms to adapt neural architectures to hardware. These algorithms will automate the process of designing networks for specific devices and tasks, while considering the different design trade-offs. The result should allow an efficient search of the Pareto front of possible solutions and come up  with novel network architectures that make the best use of available hardware. Automating this search process will enable the discovery of novel architectures, and help drive the requirements for hardware developments, enabling the co-evolution of hardware and algorithms.

The PhD Research will take place at Imec Leuven, in collaboration with the AI-lab at Vrije Universiteit Brussel (Brussels).

Imec is a world-leading research and innovation hub in nanoelectronics and digital technologies. The machine learning program at Imec is leading the quest for computationally- and energy-efficient machine learning accelerators.  By leveraging its memory technology, Imec aims to develop analog compute-in-memory (ACiM) solutions built on emerging non-volatile memory devices. These devices can mitigate the challenges related to learning algorithms, by performing the computations in the memory itself. Compared to classical Von Neumann architectures, in which computations are performed on a central processor after memory elements have been fetched from outside, compute-in-memory approaches have the promise to increase energy efficiency by orders of magnitudes, while at the same time allowing for the required high throughput. Imec‘s machine learning research is driving the co-evolution of hardware and algorithms needed to facilitate the move to this new computational paradigm

VUB’s Artificial Intelligence Lab (​​) was founded in 1983 by Luc Steels and was the first AI Lab in Europe. Under the leadership of Prof. Ann Nowé, it counts 60 researchers including 11 professors. Since its creation, the AI Lab has successfully delivered more than 50 doctoral dissertations of which 13 in the last 5 years. The lab has a publication record of more than 850 publications at major conferences and journals,, and is well embedded in the international research community. It has always had a strong focus on embodied AI, and has a solid track record in fundamental as well as applied research, both on the European level (7 EU projects in the last 5 years) and the national level. The lab has a long-standing history of research on reinforcement learning, multi-agent systems, and natural language and speech processing. Furthermore, the lab was recently enriched with researchers from the fields of computational creativity, human-AI dynamics, knowledge representation and reasoning, and constraint optimization. 

AI Lab is the driving force behind the VUB AI Experience Centre (​​). As a joint venture with three other research teams at VUB (SMIT, ETRO and Brubotics), the 800m2​ workspace is dedicated to the development of test and experience activities related to AI research and innovation, and allows the outreach to multiple stakeholders in the open innovation ecosystem (industry, policy makers, academia and the broader public). Over 20 demonstrators and prototypes are at display, while several human-centered AI test facilities are under development. The centre allows to host a part of the interactive workshops planned in the AURA project. All activities can take place in a dedicated, monitored and highly performant digital network, with access to dedicated servers or cloud infrastructure if required. 

Required background: Computer Science, Machine Learning

Type of work: 40% algorithm design, 40% experimental, 20%literature

Supervisor: Ann Nowe

Daily advisor: Peter Vrancx

The reference code for this position is 2021-065. Mention this reference code on your application form.

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