/Aligned semiconducting carbon nanotubes (CNTs) for future CMOS logic

Aligned semiconducting carbon nanotubes (CNTs) for future CMOS logic

Master projects/internships - Leuven | More than two weeks ago

Join the team that explores next generation materials for high-performance electronics.

Abstract

Aligned carbon nanotubes are a promising material candidate for next-generation field-effect transistors (FETs) due to their unique intrinsic properties (e.g. ballistic transport, excellent charge carrier mobility and high thermal conductivity). The ideal CNT material system for high-performance transistors consists of well-aligned CNTs with a consistent pitch (>250 CNTs/µm), a semiconducting purity >99.9999% and a narrow CNT diameter distribution [1,2]. Significant progress in CNT purification, assembly from solution into densely aligned arrays and subsequent integration in devices was recently shown [3-5]. This demonstrates that the CNT material remains not only scientifically attractive but offers a technologically feasible pathway towards high-performing and ultimately scaled FETs.

In this MSc work you will contribute to the development of a CNT-based platform to enable smaller footprint and better device performance with the focus on material development and characterization. You will develop competences and expertise in various techniques to characterize aligned CNT arrays, including the degree of alignment, density, purity, uniformity, CNT diameter, defects etc. in close collaboration with the Materials and Component Analysis (MCA) team at imec. Exploration of benign solutions for cleaning the CNT arrays from the polymer residue remaining from the CNT alignment and/or contamination after device fabrication might be required to improve device performance and reliability. In collaboration with the project partners from top research groups both internationally and inside imec, you will work towards true understanding of the aligned CNT material properties, quality optimization and integration to assess the CNT-based device performance.  Your MSc work will bring aligned CNT-based scaled logic transistors closer to the industry to help sustain Moore’s law beyond the physical limits of silicon.
 

Profile

As the topic focuses on the development of characterization approaches for aligned CNTs, a broad interest in different characterization methods (Raman, photoluminescence, scanning electron microscopy (SEM), surface probe microscopy (SPM), atomic force microscopy (AFM) techniques and electrical transport measurements) is preferred. A genuine interest in semiconductor physics and surface chemistry is desired.  You are a curious, independent, and resourceful person. The ability to communicate in English is a requirement in IMEC’s international environment.

Type of Project: Thesis; Combination of internship and thesis; Internship 

Master's degree: Master of Engineering Technology; Master of Engineering Science; Master of Science; Master of Bioengineering 

Master program: Materials Engineering; Nanoscience & Nanotechnology; Physics; Chemistry/Chemical Engineering 

Supervisor: Claudia Fleischmann 

For more information or application, please contact Marina Timmermans (marina.timmermans@imec.be)

 

Imec allowance will be provided. 

Who we are
Accept marketing-cookies to view this content.
Cookie settings
imec's cleanroom
Accept marketing-cookies to view this content.
Cookie settings

Send this job to your email