Analysing dynamic interaction between main memory and storage for Quality of Experience metrics in mobile consumer workloads

The heterogenous computing paradigm comprises different types of functional cores (CPU, GPU) and domain specific accelerators. Heterogeneous Computing aims to match the requirements of each application to the strengths of different compute sub-systems and achieve load balancing by avoiding idle time for both the different processing units. Heterogeneous system architectures are also becoming the norm in Mobile to Advanced driver-assistance systems (ADAS) domains. It is important to tackle the intense data traffic management demands on the underlying memory subsystem and the associated memory wall problem. An ideal design methodology should comprehend the fundamental memory streaming requirements of such a heterogenous SoC and provide necessary capabilities for optimal Quality of Experience (QoE) while ensuring the best use of available memory bandwidth and reduced impact of tail latency.

The student will be working on an application-architecture-technology co-design framework. The project will involve identifying relevant mobile workloads which require large memory footprint, understanding memory management fundamentals with respect to main memory and storage interaction and modelling a page-fault mechanism in the Ramulator (main memory simulator) framework. The student is expected to get involved with efficient design of experiments (DoE) to substantiate the simulation methodology.