Leuven | More than two weeks ago
Down scaling from one technology node to the next one becomes more challenging. This ever-increasing complexity is not only related to the downsizing of transistors, but also backend of line (BEOL) which serves as nanoscale interconnect.
BEOL scaling is required to fulfill two goals: 1) providing enough resources to connecting the FEOL elements and 2) keep pace with power and performance requirements.
To meet the first target, switching to tighter metal pitches and narrower metal lines is necessary. However, it increases both resistance and capacitance of BEOL and it consequently increase the power consumption and degrades the performance.
To overcome these problems new methods and scaling boosters are required to optimize both R and C of BEOL. Implementing boosters come with extra costs and complexities. Hence, it is important to have in depth understanding of metal distribution in BEOL to enable realistic simulations and prediction of the impact of boosters on R and C. In this regard, place and route (PnR) data are used as the reference to generate analyses based on them.
The aim of the project is to build up an automated model with PnR data as its input and comprehensive analyses of them as output. The model needs to enable the possibility to predict the impact of the BEOL boosters on R and C in a routed logic block.
Requirements to fulfil this project:
Type of project: Internship
Duration: 4 months
Required degree: Master of Engineering Technology, Master of Engineering Science
Required background: Nanoscience & Nanotechnology, Electrotechnics/Electrical Engineering
Supervising scientist(s): For further information or for application, please contact: Anita Farokhnejad (Anita.Farokhnejad@imec.be)