/Analytical modelling of 3D system design

Analytical modelling of 3D system design

Leuven | More than two weeks ago

PPA prediction model for 3D partitioning schemes
System level explorations for 3D stacking of memory and logic devices promise to leverage the flattening curve of transistor/device scaling benefits. The idea is to pack more features onto a chip and get maximal system performance ​benefits at the expense of minimal energy/area/cost.

As part of this work, we aim to develop analytical models that help us to benchmark and compare system level power, performance, area benefits resulting from 3D scaling for mobile/AI SoCs while executing compute-memory bound applications. The student is expected to work with state-of-the-art analytical models and benchmark popular DNN application workloads on different SoCs. The outcomes will help to form direct comparison with physical design parameters obtained from logic synthesis, Place and Route. In the process, the student is expected to closely work with system architects on exploring various memory/logic partitioning schemes.

Type of project: Internship, Thesis, Combination of internship and thesis

Duration: 6-9 months

Required degree: Master of Engineering Technology, Master of Science, Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering, Computer Science, Physics

Supervising scientist(s): For further information or for application, please contact: Dwaipayan Biswas (Dwaipayan.Biswas@imec.be) and Saikat Chatterjee (Saikat.Chatterjee@imec.be) and Priya Venugopal (Priya.Venugopal@imec.be)

Imec allowance will be provided.

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