PhD - Leuven | More than two weeks ago
Now that the CMOS roadmap is showing strong signs of saturation in terms of PPAC (power, performance, area and cost) figures of merit, 3D SRAM and logic integration is becoming a very attractive option. Exploiting the third dimension can result in high density ICs without requiring costly feature size reduction while also decreasing the interconnect length, which improves power and performance. However, direct stacking of multiple CMOS FEOL-BEOL layers in a sequential way does nothing for cost/transistor reduction and this presents a strong barrier to mainstream adoption. 3D NAND Flash memories have overcome this hurdle by a pure monolithic scaling process with a mask and process step scheme that is shared across all layers. However, to extend this towards SRAM and logic we see several technical and scientific challenges. Solving the coexistence of SRAM cells and logic elements in the same plane enables a new storage/computing paradigm: computation at the memory. Datapaths transforming the data flows to/from the memory locations, accelerate custom boolean functions and DSP flows, saving massive energy from the avoided data movement and speeding up workload computations. However the design of such datapaths is limited by the logic layout, imposing metal, active, and gate material lines layouts not to cross in the same plane.
In order to achieve a large enough market volume to motivate the huge NRE costs, the problem domain where such a reconfigurable coprocessor is applicable should be very broad. That requires support for advanced computational features such as SIMD, multiple and dynamic floating point formats, more complex DSP instructions, and data buffering. We need to pass instruction bits through the vertical monolithic stack to configure the computational fabric slices and that is another unsolved challenge. Several innovative technology solutions have to be explored to create such a "vertical delay line". We should not only have a solution for the logic core, but we have to add foreground memory, background data memory, instruction storage and an interface to a conventional planar processor layer for orchestration. The standard/conventional circuit and architecture techniques for these blocks must be adapted to fit into the monolithic 3D integration flow i.e., 3D Nanofabric, which is a novel 3D integration technology proposed at IMEC. This is all very novel and highly experimental.
This PhD position addresses the challenges of:
Required background: Master’s degree in electrical engineering or computer engineering with CMOS design background preferably in the design of data path, memories and/or microarchitectures.
Type of work: 20% Literature, 30% modeling, 50% design
Supervisor: Kristiaan Degreve
Co-supervisor: James Myers
Daily advisor: Fernando Garcia Redondo, Dawit Abdi
The reference code for this position is 2023-031. Mention this reference code on your application form.