Area-selective deposition: a bottom-up technique for creating nanoscale structures

Leuven - PhD
|
More than two weeks ago

You will work together with a team of deposition and lithography specialists within an international environment in a 300 mm semiconductor cleanroom using advanced tools at the leading-edge technology.

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The miniaturization of dimensions of nano-electronic device brings major challenges to the patterning process by lithography. In addition to scaling resolution, the accurate pattern placement is becoming increasingly difficult. The reduction of the active footprint also implies an evolution that involves 3D structures with high aspect ratio and complex shape. This evolution poses major challenges for the fabrication processes. Therefore, bottom-up approaches like area-selective deposition (ASD) hold great potential to complement traditional patterning for the fabrication of nano-electronic devices. In ASD, material is deposited only according to a predefined pattern, with no deposition on the rest of the surface. This can be achieved by deposition techniques that rely on selective surface reactions like atomic layer deposition (ALD) and chemical vapor deposition (CVD). ASD is a sustainable and cost effective approach that requires less chemical products and energy as compared to traditional top-down patterning. In addition, the great opportunity for ASD is that it can in principle place structures only where needed with atomic precision in both horizontal and vertical direction. ASD research and development is therefore attracting great interest from semiconductor industry.

Nevertheless, industrial applications of ASD are currently limited to selective epitaxial growth of semiconductors and metal layers in interconnect structures, mainly because up till now ASD has been studied only for a limited number of processes and materials. In addition, the inherent surface dependence of ALD and CVD processes is rarely sufficient, and a much higher selectivity is needed to enable applications in nano-electronic device fabrication. A better understanding in the surface dependence of ALD and CVD processes and the role of the precursors is essential to expand the material combinations accessible by ASD as well as to improve selectivity.

The general aim of this PhD project is to generate insight in surface dependence of ALD and CVD processes, that will guide the design of novel ASD processes and as such enable new applications. As ALD and CVD rely on surface reactions of gas phase precursors, the deposition is very sensitive to the substrate surface, which can be chemically modified to either enable or prevent growth. A first research objective is to generate detailed insight into the surface chemistry during deposition for materials relevant for future integration flows, including photoresists for Extreme Ultraviolet Lithography (EUVL), spacer materials etc. We will investigate the surface termination of the materials and study their impact on the growth and nucleation behavior during deposition. Surface treatments will be investigated to modify the surface termination and as such manipulate the surface reactivity to enable or prevent deposition. A second research objective is to apply this insight to design an ASD process, and to characterize ASD in nanoscale patterns. We will investigate the nucleation mechanisms of ASD on patterned substrates, as the selectivity might be affected by the patterning process due to changes in surface composition. In addition, exchange of species between non-growth and growth patterns can be possible due to surface or gas phase diffusion. We will leverage Imec's 300mm production line and advanced node technologies to gain access to patterned structures with dimensions down to tens of nanometers in order to industrially relevant research.  


Required background: Materials, Chemistry, Physics, Nano-electronics

Type of work: 10% literature, 90% experimental

Supervisor: Annelies Delabie

Daily advisor: Danilo De Simone

The reference code for this position is 1812-32. Mention this reference code on your application form.

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