/Area-selective deposition mechanisms when pattern dimensions reach the nanoscale

Area-selective deposition mechanisms when pattern dimensions reach the nanoscale

PhD - Leuven | More than two weeks ago

You will gain fundamental understanding that is essential to develop new processes for area-selective deposition, a bottom-up technique for creating future Logic and Memory devices.

The manufacturing processes for nano-electronic Logic and Memory devices are becoming increasingly complex due to miniaturization of device dimensions, introduction of new materials, and the use of new device architectures/concepts that involve three dimensional (3D) structures to reduce the active footprint. For example, the Complementary Field Effect Transistor (CFET) is proposed for the ultimate scaling of logic devices [1]. It consists of a compact “folded” CMOS structure with n-type and p-type FETs stacked on top of each other instead of next to each other to maintain performance under area-scaling. However, creating CFET devices poses major challenges to the conventional fabrication processes, as it requires the placement of materials in nanoscale 3D structures with complex shape and high aspect ratio, with accurate control in the horizontal and vertical direction. Bottom-up approaches like area-selective deposition (ASD) show great promise to provide solutions. ASD is a technique to deposit material only where needed on a predefined area or pattern, while no deposition occurs on adjacent surface patterns. Selectivity can be achieved by carefully tuning the adsorption and diffusion kinetics in atomic layer deposition (ALD) and chemical vapor deposition (CVD) processes [2]. The great opportunity for ASD is that it can enable the placement of material only where needed on 3D structures with the required atomic precision [3]. Moreover, ASD is a more sustainable and cost-effective approach that requires fewer chemical products and less energy as compared to traditional top-down patterning. However, until now, the industrial use of ASD has been limited to few applications (e.g. selective epitaxial growth of semiconductors, metal capping layers in interconnect structures) because high selectivity has been obtained only for a limited number of materials and processes. The ASD toolbox needs significant expansion so that we can address the current challenges in fabrication processes for Logic and Memory devices.

 

The development of novel ASD processes requires thorough understanding of the chemical and physical processes that play a role during thin film deposition, more specifically understanding of the adsorption and diffusion kinetics. The general aim of this PhD project is to generate the required insight in the growth mechanisms of metal ALD and CVD processes and use that to design novel metal ASD processes for applications in nano-electronic devices including CFET. A first research objective is to explore the adsorption and diffusion kinetics during metal ALD and CVD for materials combinations that are relevant for the novel applications. We will investigate how the surface composition of the substrate affects the metal growth and nucleation behavior. Surface treatments with small molecule inhibitors will be used to modify the surface termination to enable or prevent deposition during ALD or CVD. We will investigate the interactions of small molecule inhibitors with various substrates and precursors, revealing insight in the mechanisms of selectivity and selectivity loss. A second research objective is to apply the obtained insight to design metal ASD processes and to study the ASD mechanisms in nanoscale patterns, where the mechanism can be different than for microscale patterns or homogeneous surfaces [4]. Selectivity can be affected by diffusion, topography, and the pre-patterning process due to modified surface composition. We will leverage imec’s 300mm production line and advanced node technologies to gain access to patterned structures with dimensions down to tens of nanometers to obtain insights that are relevant for industrial applications.

[1] Entering the nanosheet transistor era | imec (imec-int.com)

[2] Grillo, F. and Soethoudt, J. et al., Chem. Mater. 2020, 32, 9560.

[3] A complementary approach to lithography | imec (imec-int.com)

[4] Clerix J.-W. J. et al., Adv. Mater. Interfaces 2021, 2100846.


Required background: Chemistry, Physics, Materials, Nanotechnology, Engineering Chemistry, Engineering Physics

Type of work: 10% literature study, 90% experimental work (depending on the interest of the student a combined experimental/theoretical investigation might be possible)

Supervisor: Annelies Delabie

Daily advisor: Annelies Delabie

The reference code for this position is 2023-043. Mention this reference code on your application form.

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