/Array-CNT with scaled pitch for high performance MOSFET applications

Array-CNT with scaled pitch for high performance MOSFET applications

PhD - Leuven | More than two weeks ago

An experimental exploration of pitch scaling limit and performance variability with dense s-CNT (single walled carbon nanotube) array field-effect transistors

Since the first carbon nano tube (CNT) transistor was demonstrated in 1998 [1], impressive progress has been achieved towards material synthesis and purification, device integration as well as high performance device demonstrations. Recent developments in array-CNT technologies [2-4] with improved CNT pitch (100~200 CNT/um) and device performance have greatly enhanced the prospect of CNTs in future CMOS (More Moore) and beyond-CMOS (More-than-Moore) applications.

In this PhD, the student will focus on device design, fabrication, electrical characterization, and the analysis of array-CNT based MOSFETs with scaled pitch (>200 CNT/um) to gain fundamental insights on:

1. Electrostatic (gate) control and pitch scaling limit: At scaled CNT-CNT pitch the inter-CNT interaction and crosstalk can degrade the sub-threshold performance, on-off ratio with an off-state current increase. Mitigation strategies such as top + bottom dual-gate design using conformal (ALD) oxides as gate dielectrics as well as the implementation of gate-all-around (GAA) designs and EOT scaling will be studied and explored for the array CNT channels with scaled CNT-CNT pitch. 

2. Device variability: While it is possible to establish links between the electrical characteristics and the physical variations in CNT arrays [5,6], more insights on the impact of alignment, density, and CNT diameter variability on transistor performance at scaled CNT-CNT pitch are needed. Here we aim to categorize and quantify the impact of the aforementioned CNT physical variations on MOSFET Vt (threshold voltage) variation through a combination of electrical and physical characterization results together with modeling effort from imec’s device modeling team.  

Additionally, engineering challenges such as contact resistance, chemically inert CNT surfaces as well as a lack of reliable CNT/insulator interface passivation schemes will be incorporated as a part of the PhD research objectives that requires extensive collaboration with dedicated researchers and device engineers at imec.

The student will start from the lab-based device platform at imec to develop competences and expertise in CNT-based device fabrication, electrical characterization and analysis. A transition to fab-based device platform is expected during the later stages of this PhD study. The student will interact closely with a variety of top research groups both inside imec and outside, with expertise in CNT purification, transfer, device processing and physical/electrical characterizations. The student will also collaborate closely with the modelling groups in imec to calibrate the models and establish the connections between CNT variability and transistor performance.

Your mission, should you decide to accept this challenge, will be to explore the array-CNT scaling limit and create a true understanding of the CNT variability-performance tradeoffs through experimental investigations to provide guidance for future CNT-based high-performance MOS technology.

[1] Nature Electronics Editorial Vol. 1, p149 (2018)

[2] Liu et al, Science 368, p. 850 (2020)

[3] Shi et al, Nature Electronics 4 (2021)

[4] Lin et al, Adv. Func. Mat., 2104539 (2021)

[5] Foradori et al, J. Appl. Phys. 128, (2020)

[6] Léonard, Nanotechnology Vol 17, p2381 (2006)

Required background: Solid state physics, material science, electrical engineering, nanoscience

Type of work: 10% literature, 70% experimental, 20% modeling

Supervisor: Valeri Afanasiev

Daily advisor: Dennis Lin

The reference code for this position is 2023-160. Mention this reference code on your application form.

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