/Array under CMOS system performance exploration

Array under CMOS system performance exploration

Leuven | More than two weeks ago

Pathfinding for next generation compute technology
CMOS technology scaling is saturating due to limited metal pitch and poly pitch scaling. Sequential 3D integration has been perceived as a promising candidate for extending Moore’s law without scaling the critical device/interconnect dimensions. Low-parasitic and high-density 3D interconnect in a sequential 3D is an attractive option for fine-grain logic and memory partitioning known as Array-under-CMOS (AuC). AuC offers an additional degree of freedom in optimizing the logic and high-speed memory separately. It further shows potential in optimizing register-file and L1-cache bandwidth and organization.

In this work, the candidate will interact with different imec groups working to identify the challenges with state-of-the-art register-file and L1-cache organization, bandwidth bottleneck between them and exploit Sequential 3D Array-under-CMOS to meet the requirements by system-level simulations.

Type of project: Combination of internship and thesis

Duration: 4-6 month

Required degree: Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering, Computer Science

Supervising scientist(s): For further information or for application, please contact: Shairfe Muhammad Salahuddin (Shairfe.Muhammad.Salahuddin@imec.be)

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