/Assembling 2D materials: Exploring a path towards stacked CFET

Assembling 2D materials: Exploring a path towards stacked CFET

PhD - Leuven | More than two weeks ago

Carving a path for 2D materials towards turbo-boosted manufacturability

Assembling 2D materials: Exploring a path towards stacked CFET


Transistor and pitch scaling has started to question the viability of silicon as the mainstream channel material for CMOS logic of the future. Active research is exploring alternative materials to provide near-term alternatives.  One promising path forward beyond CMOS logic is to develop 2D semiconductors (such as WS2, MoS2, WSe2 and Graphene) for CFET logic, where n-type and p-type transistors are stacked above each other, minimizing lateral spacing and allowing multilevel deep vias.  2D materials are an ideal candidate for such device architecture, providing one atom thick (~0.5nm) channel layers that can, in theory, provide incredibly high electron transport (>100 cm2/Vs) properties.

However, each of these materials have their own drawback from the standpoint of processing, transfer and developing intrinsic defect modes.  Further, transistors with single-layer channels of 2D have low driving voltages, therefore requiring multiple stacked channels separated by a dielectric layer.



a. Research and applicability
  1. Fundamental understanding of interfaces required for, and after 2D materials’ transfer

    Any substrates on which 2D materials are placed (as-grown or via transfer), strongly influence the performance of 2D materials.  For both graphene and TMDCs, traditional substrates such as SiO2 increases electron scattering, while atomically flat surfaces such as hexagonal boron nitride (h-BN) provide enhanced device performances.  To further complicate the matter, the performance measured in terms of mobility only gives an indirect quality assessment and provides little physical understanding of the scattering mechanisms. Extrinsic nonidealities, such as roughness, topography, surface chemistry, and contamination, among others provide several stochastic unknowns in the observed performance during their integration as interconnected devices.

  2. Enabling encapsulated 2D homo/hetero-structures

    Transistor design that implements a viable on-off voltage requires interlaced dielectric in between stacked MX2 channel layers.  Conventional heteroepitaxy processes to assemble multiple layers suffer from non-ideal growth mechanisms and severe thermal budget limitations, leaving layer-transfer as the only viable route for stacking homogeneous 2D layers.  Further, enablement of this technique can provide a route to stack, encapsulate, and interlace with alternative 2D dielectrics (such as h-BN), and conductors (such as Graphene).  Such processes not only provide an efficient means to passivate the 2D channel layer, but open multiple avenues of applicability beyond CFET logic, including photosensors and optical I/O.
b. Methods and outcomes

In this PhD project, we will tackle this challenging question by combining different defect characterization methods (e.g., optical, and electrical measurements). Novel optical measurements, based on carrier concentration-dependent photoluminescence, can quantitatively assess the density and dynamics of defect trap states in the semiconductor and its interfaces. Combined with in-situ electrical measurements, the energetic and spatial position of active defects can be studied via individual defect signatures in ultra-scaled transistors.

2D structures interact via Van der Waal’s forces. This places high degree of uncertainty towards adhesion with, and transport through other materials, including itself. Further, graphene and TMDCs are highly sensitive to the surrounding environment due to their atomically thin nature.  These nonidealities can cause unintentional doping, strain, and increased interface defectivity.  By combining distinct trapping mechanisms and studying them from different points of view, it is expected that the PhD candidate will develop a detailed understanding of the role of 2D interfaces, substrates, defects, and traps. Fundamental insight into the 2D environment will link intrinsic and extrinsic defect modes to electrical effects and enable appropriate interface-engineering to achieve low-defectivity and high device performance. 


This position is multidisciplinary and will require deep understanding of 2D material’s interfaces. Understanding the basics of semiconductor physics, solid-state physics, electrical transport, and surface chemistry is required.  A working knowledge of several characterization techniques such as photoluminescence and Raman, surface probe microscopy (SPM) is desired.  Special consideration will be given to candidates with experience in 2D material synthesis, exfoliation and/or device fabrication.  

You will be required to closely collaborate and gain expertise from several university laboratories, potentially needing to visit them at-site to learn from and use their fabrication facilities.  You are a curious, organized, independent and resourceful person. The ability to communicate fluently in English is an absolute requirement in our international environment. 


Type of work: 60% experimental (fabrication, characterization), 40% data analysis and theory

Keywords: MX2; Materials; Semiconductor Physics; Metrology & characterization

Required background: semiconductor physics, solid-state physics, electrical transport, and surface chemistry

Type of work: 60% experimental, 40% data analysis and theory

Supervisor: Stefan De Gendt

Co-supervisor: Steven Brems

Daily advisor: Souvik Ghosh

The reference code for this position is 2023-021. Mention this reference code on your application form.

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