Assembly Process Integration Engineer
What you will do
- Your mission will be to define and deliver integration flows and concepts relating to Collective Die to Wafer Bonding approaches. Your second key objective will be to contribute towards the Fine Pitch Fan Out Wafer Level Packaging development activity. Within both topics you will explore different integration concepts, working closely with our process development teams and our metrology and defectivity development teams.
- You will be responsible for discussing process splits with the characterization and/or process development engineers, as well as for the implementation of these splits into process flows.
- You plan development activities for the process modules assigned to you. You will follow-up on the processing (at both wafer and die level) of test material, collect and analyze performance data. You report results both internally as well as to customers. You will be supported in your task by a Process Assistant, but will be expected to take a significant hands on role within the clean room.
- You keep your level of scientific know-how up to date and benchmarks imec’s expertise and performance in your competence domain with the rest of the world.
- You regularly report to your team leader, program manager, program director or to the customers on progress and results as well as on new opportunities.
- You will be member of the 3DSIP Technology department where you will interact with process engineers, process assistants, test and reliability engineers as well as with industrial residents. Good communication and interaction within the 3D Technology department as well as with the CMOS technology department and Fab operations unit, is a major requirement for this job.
- You will represent Imec in contacts with third parties and representatives for semiconductor players from around the globe for matters that relate to your field of competence.
- You will operate from imec’s HQ located close to Brussels in the heart of Europe.
What we do for you
Who you are
- You have obtained a PhD or Master degree in materials science, preferably combined with some relevant industrial experience.
- You have 2-3 years experience in a semiconductor environment. A background in FBEOL processing is an asset.
- Experience in 3D stacking schemes such as Die-to-Die, Die-to-Wafer and Wafer-to-Wafer an advantage.
- Knowledge of Fan Out Wafer Level Packaging schemes is an asset.
- You have experience in presenting scientific results (publications, conferences, seminars).
- You are an enthusiastic team player with project management capabilities. You are able to complete your tasks in time with minimal supervision.
- You have good English communication skills.
- You are willing to work in a highly competitive and multicultural environment.