/Calibration of TCAD process simulators for Fin, Nanosheet and Forksheet FET devices

Calibration of TCAD process simulators for Fin, Nanosheet and Forksheet FET devices

Research & development - Leuven | More than two weeks ago

Within this project you will be at the intercept of simulation (TCAD), advanced metrology (SSRM, TEM,...) and device integration of most advanced transistors.

The aggressive downscaling of FET devices (FinFET, NanowireFET, NanosheetFET, ForksheetFET,...) in past years has put a great emphasis on the need to come up with properly calibrated process and device simulation tools to predict performances, suggest processing options and even understand failure mechanisms.  As their modeling is complex with multiple calibration parameters, adequate two- and three-dimensional (2D)-characterization techniques have been identified as a necessity for process/device engineers and for the TCAD community to achieve an accurate modeling and calibration of the complex physical mechanisms for scaled devices. In such scaled devices even the smallest variations of the structure dimensions (ie. width or length, local interconnect or spacer, source/drain epi volumes, etc.), carrier distribution and/or activation rate can cause significant variations in the electrical properties of the devices.

 

In the last years, we have demonstrated how to combine informations extracted from TEM (epi shape and volume, fin or nanowire size), EDX (epi composition in source/drain), or SSRM (2D/3D carrier maps) to successfully calibrate TCAD decks. This was performed for Si-channel FinFET devices, for instance pointing out the impact of remaining oxides after pre-epi clean in nFinFET, or of Ge content in SiGe epi S/D on the access resistance for pFinFET.  We have also implemented a simulation deck for horizontal NanowireFET device analyzing the impact of reduced carrier diffusion in the nanowires.

 

Within this project we aim at expanding this work towards even more advanced devices such as SiGe and Ge-channel devices, Nanosheet devices and Forksheet devices. Hence the student will have :

  • To utilize SSRM and its most recent mode named scalpel-SSRM (s-SSRM) to generate 2D carrier map inside GeMOS FinFET, as well as inside NanosheetFET and ForksheetFET devices (NB: Student will not have to perform measurements himself but well to understand the technique so that he can submit measurement requests)
  • To learn how to run process and device simulations using Synopsys (defining the architecture, understanding the major implantation and activation models utilized, etc.)
  • To test different possibilities to calibrate the TCAD process simulations using the SSRM 2D carrier maps (comparison between simulated and measured electrical junction positions, between 1D carrier profiles, between full 2D carrier maps,...)
  • To evaluate the quality of the calibration realized (looking at simulated vs. measured characteritics like Ion-Ioff, DIBL, Cov,…)
  • To propose modifications in the processing steps to improve the device performances



Type of project: Combination of internship and thesis

Duration: 6 months

Required degree: Master of Engineering Science, Master of Science, Master of Engineering Technology

Required background: Nanoscience & Nanotechnology, Physics

Supervising scientist(s): For further information or for application, please contact: Pierre Eyben (Pierre.Eyben@imec.be) and An De Keersgieter (An.DeKeersgieter@imec.be) and Philippe Matagne (Philippe.Matagne@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.