Calibration of TCAD process simulators towards N2 with advanced 2D/3D metrology solutions including SPM-based SSRM technique

The aggressive downscaling of FET devices (FinFET, NanowireFET, NanosheetFET, ForksheetFET, CFET...) in past years has put a great emphasis on the need to come up with properly calibrated process and device simulation tools (TCAD) to predict performances, suggest processing options and even understand failure mechanisms.

The aggressive downscaling of FET devices in past years has put a great emphasis on the need to come up with properly calibrated process and device simulation tools to predict performances, suggest processing options and even understand failure mechanisms. As their modeling is complex with multiple calibration parameters, adequate two- and three-dimensional (2D)-characterization techniques have been identified as a necessity for process/device engineers and for the TCAD community to achieve an accurate modeling and calibration of the complex physical mechanisms for scaled devices. In such scaled devices even the smallest variations of the structure dimensions (ie. width or length, local interconnect or spacer, source/drain epi volumes, etc.), carrier distribution and/or activation rate can cause significant variations in the electrical properties of the devices.

In the last years, we have demonstrated how to combine informations extracted from Transmission Electron Microscopy (epi shape and volume, fin or nanowire size), Energy Dispersive X-Ray Analysis (epi composition in source/drain), or Scanning Probe Microscopy based Scanning Spreading Resistance Microscopy (2D/3D carrier maps) to successfully calibrate TCAD decks. This was performed for Si-channel FinFET devices, for instance pointing out the impact of remaining oxides after pre-epi clean in nFinFET, or of Ge content in SiGe epi S/D on the access resistance for pFinFET. We have also implemented a simulation deck for horizontal NanowireFET device analyzing the impact of reduced carrier diffusion in very narrow nanowires.

Within this project we aim at expanding this work towards even more advanced devices such as non-Si-channel devices (SiGe, Ge, III-V), Nanosheet, Forksheet, and CFET devices that are candidates for the N2 technology node. Hence the PhD candidate will have :

• To utilize SSRM and its most recent mode named scalpel-SSRM (s-SSRM) to generate 2D carrier map for Si and other semiconductor materials, inside NanosheetFET, ForksheetFET and CFET devices.
• To evaluate possible developments of the technique as requested by the device evolutions that are introduced (vertically stacked devices, coexistence of Si with other non-Si semiconductors, increased portion of the active volume covered by metals, etc.):
  • Update the sample preparation methodology
  • Organize coexistence of low-force and high resolution SSRM, implementing force volumes sensing (i.e. new FFT modes for non-Si materials).
  • Integrate multi-probe sensing to boost SSRM resolution while controlling sub-nm removal rate depth acquisition.
  • Integrate spectroscopic I-Vs sensing for additional information at local scale on various devices (i.e., barrier height, carrier type, etc.)
• To run process and device simulations using Synopsys TCAD tools :
  • Define the different architectures
  • Evaluate the major implantation, diffusion and activation models utilized (including the impact of stress)
• To test different possibilities to calibrate the TCAD process simulations using the SSRM maps (comparison between simulated and measured electrical junction positions, between 1D carrier profiles, between full 2D carrier maps,...) as well as TEM/EDX
• To evaluate the quality of the calibration realized (looking at simulated vs. measured electrical characteristics like ION-IOFF, DIBL, Cov,…)
• To propose modifications in the processing steps (and potentially in the architectures) to improve the device performance.