2D materials are very promising to extend the logic scaling roadmap. Their atomically thin channel allows excellent electrostatic control hence further device scaling. Many single-device demonstrators have been reported in literature. However, to reach industrial adoption, fundamental understanding about defect types and their impact on performance, reliability and variability of 2D FETs are crucial . Defects form in 2D channels due to MX2 growth (e.g., dislocations, islands, grain boundary and point defects [2,3]) and fabrication-induced (e.g., MX2 transfer or interactions with environment) nonidealities. In addition, defects are also present in the gate stack (e.g., intercalated surface contaminants and oxide traps ) due to difficulties in ALD oxide nucleation and non-ideal processing.
Key aspects of this PhD
In this PhD, the student will perform electrical characterization and data analysis on 2D MOS devices to investigate the following:
- The impact of MX2 defects (impact of grain boundary and intra-grain point defects) on transistor electrical characteristics/performance. The student will gain deeper insight into the sources of defects by correlating electrical characteristics with physical characterization of individual transistors by e.g. AFM and SEM, and TCAD simulations done by other team members and researchers.
- The impact of scaling and device morphology on electrical characteristics (variability). The student will collect large datasets of electrical characteristics develop new models that describe this new class of transistors.
- Investigate the impact of MX2 defects, gate stack defects (bottom substrate and deposited top gate) and scaling of device dimensions on noise and reliability. The student will learn to use advanced measurement techniques like Time-Dependent Defect Spectroscopy (TDDS), Random Telegraph Signal (RTS) and T-dependent noise measurements to investigate which factors influence the electrical impact of traps and their energy distribution. Additionally, the student will identify whether the hysteresis, bias temperature instability (BTI), and hot-carrier degradation (HCD) are driven by the creation of novel traps or by carrier capture by pre-existing states. Furthermore, possible trap candidates will be identified and incorporated into device and transport simulators, in collaboration with the ab initio and device modeling teams at imec, and fed back to further improve device processing.
The student will work closely with 2D materials process and integration engineers to apply findings and improve the device characteristics over several learning cycles using two different and well-established device fabrication platforms. The first one is a lab-based fabrication flow which yields high-performance devices and has high flexibility in the choice of materials [5, 6]. The second is a state-of-the-art 300mm fab-based fabrication flow  for double-gated WS2 devices. Samples and wafers will be provided through 2D/beyond CMOS program.
-  Lanza, M., Smets, Q., Huyghebaert, C., & Li, L.-J. (2020). Yield, variability, reliability, and stability of two-dimensional materials based solid-state electronic devices. Nature Communications, 11(1), 5689. https://doi.org/10.1038/s41467-020-19053-9
-  Wu, P., Appenzeller, J., Stampfer, B., Waltl, M., Zhang, F., Illarionov, Y. Y., … Grasser, T. (2018). Characterization of Single Defects in Ultrascaled MoS 2 Field-Effect Transistors . ACS Nano, 12(6), 5368–5375. https://doi.org/10.1021/acsnano.8b00268
-  Song, S.H., Joo, MK., Neumann, M. et al. Probing defect dynamics in monolayer MoS2 via noise nanospectroscopy. Nat Commun 8, 2121 (2017). https://doi.org/10.1038/s41467-017-02297-3
-  Grill, A., Rzepa, G., Grasser, T., Furchi, M. M., Knobloch, T., Waltl, M., … Illarionov, Y. Y. (2016). The role of charge trapping in MoS 2 /SiO 2 and MoS 2 /hBN field-effect transistors . 2D Materials, 3(3), 035004. https://doi.org/10.1088/2053-1583/3/3/035004
-  Smets, Q., Verreck, D., Shi, Y., Arutchelvan, G., Groven, B., Wu, X., … Radu, I. (2020). Sources of variability in scaled MoS 2 FETs. In 2020 IEEE International Electron Devices Meeting (IEDM) (pp. 3.1.1-3.1.4). IEEE. https://doi.org/10.1109/IEDM13553.2020.9371890
-  Lin, D., Wu, X., Cott, D., Verreck, D., Groven, B., Sergeant, S., … Radu, I. (2020). Dual gate synthetic WS 2 MOSFETs with 120μS/μm Gm 2.7μF/cm 2 capacitance and ambipolar channel. In 2020 IEEE International Electron Devices Meeting (IEDM) (pp. 3.6.1-3.6.4). IEEE. https://doi.org/10.1109/IEDM13553.2020.9371926https://doi.org/10.1109/IEDM13553.2020.9372055
-  Asselberghs, I., Smets, Q., Schram, T., Groven, B., Verreck, D., Afzalian, A., … Radu, I. P. (2020). Wafer-scale integration of double gated WS 2 -transistors in 300mm Si CMOS fab. In 2020 IEEE International Electron Devices Meeting (IEDM) (pp. 40.2.1-40.2.4). IEEE. https://doi.org/10.1109/IEDM13553.2020.9371926
Required background: semiconductor physics, semiconductor devices, physical and electronic characterization techniques
Type of work: 15% theory, 15% modeling and simulation, 70% measurements
Supervisor: Valeri Afanasiev
Daily advisors: Quentin Smets, Ben Kaczer
The reference code for this position is 2021-140. Mention this reference code on your application form.