/Characterization of magnetic flux trapping for superconducting VLSI circuits

Characterization of magnetic flux trapping for superconducting VLSI circuits

PhD - Leuven | More than two weeks ago

Theoretical and experimental study of flux pinning in thin-films with different materials and engineered defects relevant to a multilayer IC fabrication stack

Unsustainable demand for compute power and unsustainable production hardware cost opens the door to new technology in the post-Moore era. Superconducting digital logic devices have the potential to be a large-installation digital technology positioned between state-of-art CMOS and quantum computing. The differentiating strengths of superconducting digital are energy efficiency, high computational density, and high interconnect bandwidth [1]. Imec is approaching scaling superconducting technology holistically by co-developing fabrication process, logic, memory, and interconnects driven by system architecture studies. 


Variability cooldown to cooldown is the signature of parasitic flux failures, which can be either flux trapping in the ground plane or persistent current trapping in the circuit itself [2-3]. This has historically been a serious limiting issue. While understandings have improved as circuit scale and complexity have increased, the best methods of parasitic flux mitigation have not been fully implemented due to limitations imposed by materials and fabrication processes.


In this PhD research, you will investigate effective flux-trap engineering techniques as function of material stability and control, and patterning. A systematic approach is needed for characterization of material parameters using transport techniques, magnetic imaging [4], and design of functional-circuit test vehicles. The experimental work needs to be complemented by developing a simulation package based on Ginzburg-Landau potentials [5]. You will interact closely with top researchers in superconductivity at imec, in magnetic imaging at Cornell University, and materials research at Jefferson Lab. 

Characterization of magnetic flux trapping for superconducting VLSI circuits

[1] Q. P. Herr, A. Y. Herr, O. T. Oberg, and A. G. Ioannidis, “Ultra-low-power superconductor logic,” Journal of applied physics, vol. 109, no. 10, p. 103903, 2011.

[2] V. Shmidt and G. Mkrtchyan, “Vortices in type-II superconductors,” Soviet Physics Uspekhi, vol. 17, no. 2, p. 170, 1974.

[3] G. Stan, S. B. Field, and J. M. Martinis, “Critical field for complete vortex expulsion from narrow superconducting strips,” Physical review letters, vol. 92, no. 9, p. 097003, 2004.

[4] J. Kirtley, “Fundamental studies of superconductors using scanning magnetic imaging,” Reports on Progress in Physics, vol. 73, no. 12, p. 126501, 2010.

[5] I. Sadovskyy, A. Koshelev, C. L. Phillips, D. A. Karpeyev, and A. Glatz, “Stable large-scale solver for Ginzburg–Landau equations for superconductors,” Journal of Computational Physics, vol. 294, pp. 639–654, 2015.


Required background: Solid-State Physics, Statistics, Matlab or equivalent, Material science


Type of work: 70% modelling/simulation, 30% experimental

Supervisor: Margriet Van Bael

Co-supervisor: Anna Herr

Daily advisor: Anna Herr

The reference code for this position is 2023-116. Mention this reference code on your application form.

Who we are
Accept marketing-cookies to view this content.
Cookie settings
imec's cleanroom
Accept marketing-cookies to view this content.
Cookie settings

Send this job to your email