/Chip – Interposer Co-design for sub-terahertz 6G Applications

Chip – Interposer Co-design for sub-terahertz 6G Applications

PhD - Leuven | More than two weeks ago

You will improve the performance of sub-THz ICs by co-designing them with high-quality off-chip passive components from the interposer that carries the chip.

Waferscale silicon interposer technology is a well-established interconnect solution for digital systems like microprocessors, high bandwidth memory and chip-to-chip communication. With the expected increase of carrier frequencies in 6G wireless communication beyond 100 GHz, there is tremendous interest to explore if the solutions developed for digital systems are also applicable to RF systems.


At such high frequencies two fundamental challenges appear for electronic systems. First, passive interconnect solutions based on PCBs incur excessively high loss and signal leakage. Secondly, active integrated circuits for frequency and power generation becomes challenging as the operating frequencies are approaching the cut-off frequency of the transistors on the chip.


Imec has developed a heterogeneous integration platform based on Si-interposer technology on which various discrete RF components, integrated passives and ICs can be integrated. This highly miniaturized platform is also able to scale to very high frequencies.


The passive components on the interposer are typically less lossy than the equivalent components on the chip. However, the transition from the chip to the interposer can come with parasitics that can degrade circuit performance and bandwidth. In this PhD work, you will explore how various critical building blocks of a 140 GHz communication transceiver can exploit the chip-interposer combination to improve performance compared to a fully on-chip circuit.


During your PhD career at imec you will be embedded in a team with designers of active and passive RF and mm-wave circuits and components. You will also have access to imec’s world class R&D fab to realize you designs as well as tweak the underlying technology parameters. We also have a fully equipped RF Lab where you can perform different measurements to validate your designs.

Required background: Electrical Engineering

Type of work: 60% modeling/simulation, 30% experimental, 10% literature

Supervisor: Piet Wambacq

Daily advisor: Siddhartha Sinha

The reference code for this position is 2023-085. Mention this reference code on your application form.

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