Circuit and System Level Exploration of Sequential 3D Technology

Leuven - PhD
More than two weeks ago

Identifying the possibility of imec sequential 3D technology in post-Moore era.

Logic scaling is getting harder and harder. As CMOS scales down to node N5 and beyond, gate length scaling becomes increasingly difficult if not impossible. The combined challenge of the gate and contact scaling has highlighted the need for innovation in device architecture and circuit design imperative. In this PhD would require to investigate different sequential 3D technology options from circuits and system perspective and guide the process development team in right directions. 



Required background: Electronic and computer engineering


Type of work: 50% modeling, 30% simulation, 20% literature

Supervisor: Francky Catthoor

Daily advisor: Shairfe Muhammad Salahuddin

The reference code for this position is 1812-85. Mention this reference code on your application form.


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