You will investigate the world of computer devices that empower now-a-days communication devices and will enable the internet of things (IOT). You will work on stacking different computer components in single packages. This is done by advanced packages or 3D integration. To enable the stacking of the components they need to be electrically connected, which is achieved by attaching bumps on one component to pads on a second component.
You will study how to efficiently remove residuals from the surface of computer chips (dies) that are stacked on a carrier wafer. The specific challenges lay in the topography due to the dies stacked on the wafer and the intermix of different materials. These include silicon, metals – like copper – and temporary bonding material (glue).
You will start working on beaker level to study cleaning of computer dies attached to carrier wafers. The results will be studied including light microscope, FTIR, SEM, etc. Successful cleaning candidates will be tests on state of the art cleaning tools in IMEC own 300 mm chip fabric and can potentially become part of the pilot plant production.
The cleaning of these dies will give insights into the interaction of resist on top of the dies, the glue – or temporary bonding material (TBM) – holding the dies on the carrier and the particles created by previous process steps with different cleaning formulations and solvents to remove all these components.
Type of project: Internship; Thesis; Combination of internship and thesis
Duration: minimum 3 months
Required degree: Master of Engineering Technology; Master of Science; Master of Engineering Science
Required background: Chemistry/Chemical Engineering; Materials Engineering; Nanoscience & Nanotechnology; Physics
Supervising scientist: For further information or for application, please contact Simon Braun (email@example.com).
Imec allowance will be provided for students studying at a non-Belgian university.