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Complementary and IGZO TFT technology feasibility circuit design
Leuven | More than two weeks ago
Improving circuit blocks by introducing very low leakage transistors
A student will make a design using IGZO transistors in a complementary technology (Si CMOS or LTPS TFT) to improve the performance and the footprint of the design. Besides the vertical integration that will increase the footprint of the design, the very low off-leakage current of IGZO-TFT could potentially not only scale down but also improve the overall perfomance of the circuit block. Moreover, in this designs the student will take advantage of two n-mos transistors with different characteristics: n-type Si transistors(or LTPS TFT) with >10x mobility of IGZO-TFT and IGZO-TFTs with >1000x lower leakage off-current. A rather complex test vehicle of an ADC will be used to measure the performance improvement after the introduction of the low-leakage transistors.
Type of project: Internship, Combination of internship and thesis
Duration: 12
Required degree: Master of Engineering Technology, Master of Engineering Science
Supervising scientist(s): For further information or for application, please contact: Nikolas Papadopoulos (Nikolas.Papadopoulos@imec.be)
Imec allowance will be provided.