/Computer Architecture Modeling with focus on Cache/Memory Subsystem

Computer Architecture Modeling with focus on Cache/Memory Subsystem

Leuven | More than two weeks ago

Modeling and evaluating cutting edge computer architecture with software simulation frameworks, with a focus on memory hierarchy (i.e., not processor microarchitecture)
High-level event-driven simulation frameworks like Gem5 (gem5.org), SST (sst-simulator.org) play a crucial role in computer architecture research both in academia/industry, wherein, one implements microarchitectural ideas as software models, followed by evaluating their system-level impact through simulation with realistic workloads. 

If you are interested in
state-of-the-art computer architecture modeling research and in developing novel architecture ideas, please apply.  Some of the topics of interest are (but not limited to):
 
  • Memory consistency and coherency study  

  • NOC/Interconnect component modeling 

  • Cache modeling (e.g., Cache replacement policy design and exploration etc.) 

 

The prospective candidate needs to have strong background in computer architecture and C++ programming; familiarity with parallel programming (e.g., MPI) is a plus.  



Type of project: Thesis, Internship

Duration: 6 or 9 months

Required degree: Master of Engineering Science

Required background: Computer Science, Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Sayandip De (Sayandip.De@imec.be) and Vinay Kumar Baapanapalli Yadaiah (Vinay.Kumar.BaapanapalliYadaiah@imec.be)

Imec allowance will be provided.

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