Conversion of design verification decks from Calibre to PVS

Leuven - Master projects/internships
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More than two weeks ago

The purpose of this work is to convert an existing design verification flow based on Calibre verification tool (Mentor Graphics) to PVS from Cadence. This will be done in the context of the design hardened against radiations for space mission.

The purpose of this work is to convert an existing design verification flow based on Calibre verification tool (Mentor Graphics) to PVS from Cadence. This will be done in the context of the design hardened against radiations for space mission.

IMEC IC-link has developed in the past several libraries hardened against radiation (DARE libraries). These libraries are provided to the end-user with extra deck rules to verify that the complete chip (i.e. with also part not coming from an imec DARE library) is compliant with the design rule of RadHard design.

 

Software used:

         Cadence Virtuoso (schema & layout), PVS

         Linux OS

Time allocation:

         20% studying literature

         80% coding/scripting

Type of project: Internship

Duration: 6 weeks or more

Required degree: Master of Engineering Technology, Master of Engineering Science

Supervising scientist(s): For further information or for application, please contact: Staf Verhaegen (Staf.Verhaegen@imec.be)

Only for self-supporting students.

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