Coupled oscillator network for low-noise GHz-to-millimeter-wave frequency synthesis on CMOS

Emerging GHz-to-millimeter-wave wireless communication systems, with increasing carrier frequencies and complex modulation schemes, require local oscillators (LOs) with better spectral purity. In other words, performance of such transceivers is significantly limited by the LO phase noise (PN). One of the most significant contributors to phase noise is the oscillator integrated within the LO synthesizer. While different design techniques are available to lower the phase noise of an integrated oscillator (trading off with power consumption and area), yet there are limitations due to technology (e.g. transistor noise and quality factor of metallization).

Coupled oscillators overcome such limitations. At the expense of area, several oscillatory cores synchronize to each other and coherently enlarge their signal-to-noise (SNR) ratio. Compared to a single core, N synchronized cores exhibit a phase noise reduction with a factor N. Of course, the design of such a synchronized network acquires some more complexity, especially due to the danger of parasitic multi-mode oscillations. On the recent attention to this kind of circuits, notice that the entire session 8 (entitled “GHz-to-Millimeter Wave Frequency Generation”) of the 2023 edition of the International Solid-State Circuit Conference (premier conference in its field) focuses on multi-core oscillators [1][2][3][4].

This MSc thesis will focus on the investigation and design of a multi-core oscillatory network in a 22 nm Fully-Depleted SOI CMOS technology. Targeting, as first application, D-Band (140-GHz) communication, and foreseeing frequency multipliers, the oscillator network will be designed at a subharmonic (e.g. 140/3 or 140/9 GHz).  You will be guided by and work within a team of experts in RFIC design, within the Advanced RF group of imec Leuven. Attention will be given to a first literature study and feasibility study. Then, you will design the multi-core network, with attention on both actives (transistors) and passives (transmission lines, inductors, transformers, capacitors). You will validate performance with simulations and possibly will also contribute to the layout (meant for, possibly, fabrication of a test chip). For this topic, an internship of at least six months (ideally eight or nine) is desirable.

Type of Project: Combination of internship and thesis 

Master's degree: Master of Engineering Science 

Master program: Electrotechnics/Electrical Engineering 

Duration: 8 months 

Supervising scientists: Giovanni Mangraviti, Sriram Balamurali, Piet Wambacq 

For more information or application, please contact Giovanni Mangraviti (giovanni.mangraviti@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.