/Creating Advanced gate stacks for 2D semiconductor devices

Creating Advanced gate stacks for 2D semiconductor devices

PhD - Leuven | More than two weeks ago

You will build fundamental understanding that contributes to the development of innovative and industrially relevant solutions for 2D material devices
Two-dimensional (2D) materials, with graphene as most famous representative, are an interesting class of materials due to their ultra-thin body nature. Inorganic 2D materials can exhibit either insulating, metallic, semi-metallic or semiconducting properties, depending on the composition and structure. The semiconducting 2D materials like WS2, MoS2 and WSe2 attract great interest for application in nano-electronic beyond silicon devices, in view of their monolayer thickness, large band gap values, low dielectric constants, structural stability and self-passivating nature of the basal plane [1,2]. One of the challenges for implementation in devices is creating the nm-thin insulating layers on the 2D semiconductor. Atomic Layer Deposition (ALD) has been widely used for the deposition of ultrathin gate dielectric films in silicon technology. However, the inherent self-passivated nature of 2D material surface complicates the formation of nm-thin insulating layers by this technique. In addition, because of their atomic scale thickness, the charge transport in 2D semiconductors depends to a large extend on the external surroundings. The interfaces will govern the electronic performance for a big part and require intensive research in view of scaling the gate dielectric thickness while maintaining the channel transport properties.

A first objective of this PhD project is to study new materials and new process strategies, beyond conventional ALD, for forming the interface layer and the gate dielectric on 2D channels and the impact on dielectric properties and transport. We will first investigate the impact of several amorphous and 2D dielectric materials on the transport properties into the channel using back gate architecture, in collaboration with device team. Based on the results, we will select the most promising materials for further investigation. Next, we will investigate the growth mechanism during deposition on a 2D semiconductor surface, and investigate how it affects the layer closure and structure of the resulting interface. The initial growth mechanism is governed by a complex interplay of processes, including physisorption, chemisorption, diffusion, aggregation, and possibly crystallization [3,4]. Information about the growth evolution comes from an extensive set of characterization techniques available in the imec labs and facilities. The properties of the selected deposited dielectric layers, the resulting interface with the 2D semiconductor and its performance in electrical devices will be tested in collaboration with the beyond CMOS device team at imec.

A second research objective is to identify and address some of the specific material and deposition technological and scientific challenges at small scale, in view of forming ultimately the gate dielectric at the dimension of sub 10 nm device. Specific attention will go to the opportunities offered by area-selective deposition techniques with 2D materials and the gate stack realm.

1] M. Chhowalla, H. S. Shin, G. Eda, L.-J. Li, K. P. Loh and H. Zhang, Nature Chemistry, 5, 263 (2013).

[2] B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, A. Kis, Nature Nanotechnology, 6, 147 (2011).

[3] J. Soethoudt, F. Grillo, E. A. Marques, J. R. van Ommen, Y. Tomczak, L. Nyns, S. van Elshocht, A. Delabie, Advanced Materials Interfaces, 5, 1800870 (2018)

[4] H. Zhang, G. Arutchelvan, J. Meersschaut, A. Gaur, T. Conard, H. Bender, D. Lin, I. Asselberghs, M. Heyns, I. Radu, W. Vandervorst, A. Delabie, Chemistry of Materials, 2017, 29, 6772.

Required background: Material science, Chemistry, Nanotechnology, Physics

Type of work: 10% literature 90% experimental

Supervisor: Annelies Delabie

Daily advisor: Pierre Morin

The reference code for this position is 2023-016. Mention this reference code on your application form.

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