Cross-layer memory simulation and architecture exploration framework

Leuven - Master projects
About a week ago

Learn at imec and at ETH Zurich how emerging memory technologies can change tomorrow's computer architectures

At imec, we are developing a cross-layer simulator framework (entitled SEAT: System benchmarking for Enablement of Advanced Technologies) intended to exploring a wide variety of memory organisations/architectures and application domain targets with different characteristics. Until now, we have mainly worked on the cache hierarchy and main memory organisation. This endeavour was carried out in close cooperation with university groups. Now we want to extend this framework to include also the protocols beyond the main memory level. For this purpose we want to collaborate closely with the group of Prof. Onur Mutlu at ETHZurich in Switzerland. This extension will be particularly useful in evaluating the impact of emerging non-volatile memories like Ferro-electric RAM, CBRAM, PCM at the storage class memory (SCM) level. For this purpose, the current simulator framework has to be further extended and validated with relevant academic/commercial benchmarks.


The MSc thesis focus will be on this extension, and it will especially involve working on the software framework, system architecture and incorporation of the different non-volatile memory models. The activity will happen partly at imec, Leuven and partly at ETHZ, Zurich, in close cooperation with the team of Prof. Onur Mutlu. So it will involve a stay outside Belgium (3 months).‚Äč

Type of project: Thesis, Combination of internship and thesis

Duration: 6-9 months

Required degree: Master of Engineering Technology, Master of Science

Required background: Computer Science, Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Timon Evenblij ( and Manu Perumkunnil ( and Francky Catthoor (

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