Defect Modeling and Manufacturing Test of STT-MRAM

Magnetic tunnel junctions (MTJs) are special devices made of ferromagnet/insulator/ferromagnet trilayers, in which the relative magnetizations of the two magnetic layers is tuned to store one bit of information. MTJs are the basic storage element from which we can build STT-MRAMs (spin-transfer torque magnetic random-access memories). Due to the MTJ properties, STT-MRAM offers, in comparison with conventional memories, competitive write performance, endurance, retention, and power consumption [1]. The tunability of these aspects makes STT-MRAMs customizable both as embedded memory solution (potentially replacing SRAMs) as well as discrete memory solution (potentially replacing DRAMs). These properties allow STT-MRAMs to be useful in a variety of applications such as Internet-of-Things (IoT), automotive, aerospace, and last-level caches [1]. Consequently, STT-MRAM technology has recently received a large amount of attention for commercialization from major semiconductor companies such as Intel [2] and Samsung [3].

Manufacturing processes of integrated circuits (ICs), including those based on STT-MRAM devices, usually involve several fabrication steps that require high precision, and hence are also ‘defect’-prone. Defects can be classified as global (occurring over the entire wafer; due to mask misalignment, for example) or local ‘spot’ (dust on IC, material stack imperfections, etc) defects. Because spot defects might occur as a ‘lone wolf’ at virtually any place in the IC, detecting them can be compared to searching for the proverbial “needle-in-the-haystack”. Defect creation during fabrication can result in reduced wafer yield and poor device performance, amongst others. Hence, it is important to identify the sources of such defects by developing appropriate defect models, fault primitives, test algorithms and routines.  

This PhD will focus on the study of defects in STT-MRAM devices fabricated in imec’s state-of-the-art 300mm pilot line. Conventional research has modelled defects in STT-MRAM devices as linear resistors, but this has resulted in creation of defect models for non-existent defects, and thus poor fault-testing routines. Thus, there is a need to understand the fundamental mechanisms of STT-MRAM devices and its unique failure mechanisms to develop device-aware test (DAT) routines [4, 5].

This PhD research will focus on the following tasks -

• Experimental identification of failure mechanisms in STT-MRAMs, by measurement and characterization
• Development of accurate spice-based models for defective devices
• Analyzing the impact of the defect on the functional behavior of the memory
• Development of a combined defect model and consequently, test solutions and design-for-testability circuits for STT-MRAM technology.
• You will be part of a collective effort: strong interaction with device technology engineers and other modelling experts is expected and encouraged

In the first phase, the student will perform extensive literature search on the existing methodologies of defect identification, modelling and test solution development, specifically for STT-MRAM technology. The student is expected to understand and assimilate the shortcomings of the conventional methods, and the need for a device-aware approach. In parallel, the student will be expected to learn and develop software routines (Python or Matlab) for data post-processing and modelling activities. With the in-depth knowledge gained, the following phases will involve the tasks detailed above.

References

1. Manu Komalan et al., “Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems” in Proceedings 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, May 2017, pp. 1–4, doi:10.1109/ISCAS.2017.8050923
2. L. Wei et al., “A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique”, in 2019 Proceedings IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, March  2019, pp. 214–216, doi:10.1109/ISSCC.2019.8662444
3. K. Lee et al., “1Gbit High Density Embedded STT-MRAM in 28nm FDSOI Technology” in Proceedings 2019 IEEE International Electron Devices Meeting (IEDM), December 2019, pp. 2.2.1–2.2.4, doi:10.1109/IEDM19573.2019.8993551
4. L. Wu et al., “Defect and Fault Modeling Framework for STT-MRAM Testing”, in IEEE Transactions on Emerging Topics in Computing, pp. 1–1, December 2019, doi:10.1109/TETC.2019.2960375
5. L. Wu et al., “Electrical Modeling of STT-MRAM Defects”, in Proceedings 2018 IEEE International Test Conference (ITC), Phoenix, AZ, USA, October 2018, pp. 1–10, doi:10.1109/TEST.2018.8624749