PhD - Leuven | More than two weeks ago
Making STT-MRAMs Production-Worthy
Magnetic tunnel junctions (MTJs) are special devices made of ferromagnet/insulator/ferromagnet trilayers, in which the relative magnetizations of the two magnetic layers is tuned to store one bit of information. MTJs are the basic storage element from which we can build STT-MRAMs (spin-transfer torque magnetic random-access memories). Due to the MTJ properties, STT-MRAM offers, in comparison with conventional memories, competitive write performance, endurance, retention, and power consumption . The tunability of these aspects makes STT-MRAMs customizable both as embedded memory solution (potentially replacing SRAMs) as well as discrete memory solution (potentially replacing DRAMs). These properties allow STT-MRAMs to be useful in a variety of applications such as Internet-of-Things (IoT), automotive, aerospace, and last-level caches . Consequently, STT-MRAM technology has recently received a large amount of attention for commercialization from major semiconductor companies such as Intel  and Samsung .
Manufacturing processes of integrated circuits (ICs), including those based on STT-MRAM devices, usually involve several fabrication steps that require high precision, and hence are also ‘defect’-prone. Defects can be classified as global (occurring over the entire wafer; due to mask misalignment, for example) or local ‘spot’ (dust on IC, material stack imperfections, etc) defects. Because spot defects might occur as a ‘lone wolf’ at virtually any place in the IC, detecting them can be compared to searching for the proverbial “needle-in-the-haystack”. Defect creation during fabrication can result in reduced wafer yield and poor device performance, amongst others. Hence, it is important to identify the sources of such defects by developing appropriate defect models, fault primitives, test algorithms and routines.
This PhD will focus on the study of defects in STT-MRAM devices fabricated in imec’s state-of-the-art 300mm pilot line. Conventional research has modelled defects in STT-MRAM devices as linear resistors, but this has resulted in creation of defect models for non-existent defects, and thus poor fault-testing routines. Thus, there is a need to understand the fundamental mechanisms of STT-MRAM devices and its unique failure mechanisms to develop device-aware test (DAT) routines [4, 5].
This PhD research will focus on the following tasks:
You will be part of a collective effort: strong interaction with device technology engineers and other modelling experts is expected and encouraged.
In the first phase, the student will perform extensive literature search on the existing methodologies of defect identification, modelling and test solution development, specifically for STT-MRAM technology. The student is expected to understand and assimilate the shortcomings of the conventional methods, and the need for a device-aware approach. In parallel, the student will be expected to learn and develop software routines (Python or Matlab) for data post-processing and modelling activities. With the in-depth knowledge gained, the following phases will involve the tasks detailed above.
During the four-year PhD project, the PhD student will spend roughly 50% of his/her time at TU Delft and the other 50% at IMEC in Leuven, Belgium.
Supervisor: Said Hamdoui (TU Delft)
Daily advisors: Erik Jan Marinissen (imec), Siddharth Rao (imec)
Location: Leuven & Delft
Focus of work: Devices;#Modeling;#Circuit Design;#Metrology & characterization
The reference code of this topic is 2021-013. Please mention this on your application.
The next application window will be open from mid-March 2021 until mid-April 2021.
It is not possible to send in your application before mid-March 2021.